xref: /linux/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml (revision 762f99f4f3cb41a775b5157dd761217beba65873) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: System Reset Controller on Intel Gateway SoCs
8
9maintainers:
10  - Dilip Kota <eswara.kota@linux.intel.com>
11
12properties:
13  compatible:
14    enum:
15      - intel,rcu-lgm
16      - intel,rcu-xrx200
17
18  reg:
19    description: Reset controller registers.
20    maxItems: 1
21
22  intel,global-reset:
23    description: Global reset register offset and bit offset.
24    $ref: /schemas/types.yaml#/definitions/uint32-array
25    items:
26      - description: Register offset
27      - description: Register bit offset
28        minimum: 0
29        maximum: 31
30
31  "#reset-cells":
32    minimum: 2
33    maximum: 3
34    description: |
35      First cell is reset request register offset.
36      Second cell is bit offset in reset request register.
37      Third cell is bit offset in reset status register.
38      For LGM SoC, reset cell count is 2 as bit offset in
39      reset request and reset status registers is same. Whereas
40      3 for legacy SoCs as bit offset differs.
41
42required:
43  - compatible
44  - reg
45  - intel,global-reset
46  - "#reset-cells"
47
48additionalProperties: false
49
50examples:
51  - |
52    rcu0: reset-controller@e0000000 {
53        compatible = "intel,rcu-lgm";
54        reg = <0xe0000000 0x20000>;
55        intel,global-reset = <0x10 30>;
56        #reset-cells = <2>;
57    };
58
59    pwm: pwm@e0d00000 {
60        compatible = "intel,lgm-pwm";
61        reg = <0xe0d00000 0x30>;
62        clocks = <&cgu0 1>;
63        #pwm-cells = <2>;
64        resets = <&rcu0 0x30 21>;
65    };
66