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/linux/arch/x86/include/asm/uv/
H A Duv_mmrs.h555 unsigned long lb_hcerr:1; /* RW */
561 unsigned long lb_hcerr:1; /* RW */
563 unsigned long rh_hcerr:1; /* RW */
564 unsigned long lh0_hcerr:1; /* RW */
565 unsigned long lh1_hcerr:1; /* RW */
566 unsigned long gr0_hcerr:1; /* RW */
567 unsigned long gr1_hcerr:1; /* RW */
568 unsigned long ni0_hcerr:1; /* RW */
569 unsigned long ni1_hcerr:1; /* RW */
570 unsigned long lb_aoerr0:1; /* RW */
[all …]
/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_rf2959.c32 static int bits(u32 rw, int from, int to)
34 rw &= ~(0xffffffffU << (to+1));
35 rw >>= from;
36 return rw;
39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
44 static void dump_regwrite(u32 rw)
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
[all …]
H A Dmeson_dw_mipi_dsi.h13 * [3] RW timing_rst_n: Default 1.
15 * [2] RW dpi_rst_n: Default 1.
17 * [1] RW intr_rst_n: Default 1.
19 * [0] RW dwc_rst_n: Default 1.
30 * [4] RW manual_edpihalt: Default 0.
32 * [3] RW auto_edpihalt_en: Default 0.
35 * [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
38 * [1] RW enable_pixclk: A manual clock gate option, due to DWC IP does not
40 * [0] RW enable_sysclk: A manual clock gate option, due to DWC IP does not
49 * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
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/linux/include/linux/mfd/
H A Dkhadas-mcu.h36 #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
37 #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
38 #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
39 #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
40 #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
41 #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
42 #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
43 #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
44 #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
45 #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
[all …]
H A Dstmfx.h16 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
18 #define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */
19 #define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */
21 #define STMFX_REG_IRQ_ACK 0x44 /* RW */
29 #define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */
30 #define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */
31 #define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */
32 #define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */
33 #define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */
34 #define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
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/linux/fs/smb/client/
H A Ddfs.h46 struct dfs_ref_walk *rw; in ref_walk_alloc() local
48 rw = kmalloc(sizeof(*rw), GFP_KERNEL); in ref_walk_alloc()
49 if (!rw) in ref_walk_alloc()
51 return rw; in ref_walk_alloc()
54 static inline void ref_walk_init(struct dfs_ref_walk *rw) in ref_walk_init() argument
56 memset(rw, 0, sizeof(*rw)); in ref_walk_init()
57 ref_walk_cur(rw) = ref_walk_start(rw); in ref_walk_init()
70 static inline void ref_walk_free(struct dfs_ref_walk *rw) in ref_walk_free() argument
74 if (!rw) in ref_walk_free()
77 for (ref = ref_walk_start(rw); ref <= ref_walk_end(rw); ref++) in ref_walk_free()
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H A Ddfs.c86 struct dfs_ref_walk *rw, in parse_dfs_target() argument
90 const char *fpath = ref_walk_fpath(rw) + 1; in parse_dfs_target()
92 rc = ref_walk_get_tgt(rw, tgt); in parse_dfs_target()
100 struct dfs_ref_walk *rw) in setup_dfs_ref() argument
121 ref_walk_path(rw) = ref_path; in setup_dfs_ref()
122 ref_walk_fpath(rw) = full_path; in setup_dfs_ref()
123 ref_walk_ses(rw) = ctx->dfs_root_ses; in setup_dfs_ref()
128 struct dfs_ref_walk *rw) in __dfs_referral_walk() argument
136 ctx->dfs_root_ses = ref_walk_ses(rw); in __dfs_referral_walk()
137 if (ref_walk_empty(rw)) { in __dfs_referral_walk()
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
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/linux/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
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/linux/block/
H A Dblk-throttle.c91 static uint64_t tg_bps_limit(struct throtl_grp *tg, int rw) in tg_bps_limit() argument
98 return tg->bps[rw]; in tg_bps_limit()
101 static unsigned int tg_iops_limit(struct throtl_grp *tg, int rw) in tg_iops_limit() argument
108 return tg->iops[rw]; in tg_iops_limit()
241 int rw; in throtl_pd_alloc() local
255 for (rw = READ; rw <= WRITE; rw++) { in throtl_pd_alloc()
256 throtl_qnode_init(&tg->qnode_on_self[rw], tg); in throtl_pd_alloc()
257 throtl_qnode_init(&tg->qnode_on_parent[rw], tg); in throtl_pd_alloc()
310 int rw; in tg_update_has_rules() local
312 for (rw = READ; rw <= WRITE; rw++) { in tg_update_has_rules()
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/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
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/linux/arch/arc/include/asm/
H A Dspinlock.h79 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
87 * if (rw->counter > 0) { in arch_read_lock()
88 * rw->counter--; in arch_read_lock()
101 : [rwlock] "r" (&(rw->counter)), in arch_read_lock()
109 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
125 : [rwlock] "r" (&(rw->counter)), in arch_read_trylock()
134 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
144 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_lock()
145 * rw->counter = 0; in arch_write_lock()
158 : [rwlock] "r" (&(rw->counter)), in arch_write_lock()
[all …]
/linux/io_uring/
H A Drw.c24 #include "rw.h"
50 static int io_iov_compat_buffer_select_prep(struct io_rw *rw) in io_iov_compat_buffer_select_prep() argument
55 uiov = u64_to_user_ptr(rw->addr); in io_iov_compat_buffer_select_prep()
63 rw->len = clen; in io_iov_compat_buffer_select_prep()
72 struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); in io_iov_buffer_select_prep() local
74 if (rw->len != 1) in io_iov_buffer_select_prep()
79 return io_iov_compat_buffer_select_prep(rw); in io_iov_buffer_select_prep()
82 uiov = u64_to_user_ptr(rw->addr); in io_iov_buffer_select_prep()
85 rw->len = iov.iov_len; in io_iov_buffer_select_prep()
94 struct io_rw *rw = io_kiocb_to_cmd(req, struct io_rw); in __io_import_iovec() local
[all …]
/linux/arch/parisc/include/asm/
H A Dspinlock.h79 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
85 arch_spin_lock(&(rw->lock_mutex)); in arch_read_trylock()
91 if (rw->counter > 0) { in arch_read_trylock()
92 rw->counter--; in arch_read_trylock()
96 arch_spin_unlock(&(rw->lock_mutex)); in arch_read_trylock()
103 static inline int arch_write_trylock(arch_rwlock_t *rw) in arch_write_trylock() argument
109 arch_spin_lock(&(rw->lock_mutex)); in arch_write_trylock()
117 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_trylock()
118 rw->counter = 0; in arch_write_trylock()
121 arch_spin_unlock(&(rw->lock_mutex)); in arch_write_trylock()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_regs.h8 #define IGC_CTRL 0x00000 /* Device Control - RW */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
14 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
15 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */
20 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
21 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
24 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
[all …]
/linux/Documentation/hwmon/
H A Damc6821.rst30 temp1_min rw "
31 temp1_max rw "
32 temp1_crit rw "
38 temp2_min rw "
39 temp2_max rw "
40 temp2_crit rw "
47 fan1_min rw "
48 fan1_max rw "
50 fan1_pulses rw Pulses per revolution can be either 2 or 4.
51 fan1_target rw Target fan speed, to be used with pwm1_enable
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-hwmon25 RW
36 RW
44 RW
56 RW
64 RW
150 RW
175 RW (but changing it should no more be necessary)
206 RW
215 RW
231 RW
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/linux/drivers/char/mwave/
H A D3780i.h68 unsigned char ClockControl:1; /* RW: Clock control: 0=normal, 1=stop 3780i clocks */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
70 unsigned char ConfigMode:1; /* RW: Configuration mode, 0=normal, 1=config mode */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
79 unsigned short DiagnosticMode:1; /* RW: Disgnostic mode 0=nromal, 1=diagnostic mode */
96 unsigned char IrqActiveLow:1; /* RW: IRQ active high or low: 0=high, 1=low */
97 unsigned char IrqPulse:1; /* RW: IRQ pulse or level: 0=level, 1=pulse */
98 unsigned char Irq:3; /* RW: IRQ selection */
[all …]
/linux/arch/sh/include/asm/
H A Dspinlock-cas.h52 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
55 do old = rw->lock; in arch_read_lock()
56 while (!old || __sl_cas(&rw->lock, old, old-1) != old); in arch_read_lock()
59 static inline void arch_read_unlock(arch_rwlock_t *rw) in arch_read_unlock() argument
62 do old = rw->lock; in arch_read_unlock()
63 while (__sl_cas(&rw->lock, old, old+1) != old); in arch_read_unlock()
66 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
68 while (__sl_cas(&rw->lock, RW_LOCK_BIAS, 0) != RW_LOCK_BIAS); in arch_write_lock()
71 static inline void arch_write_unlock(arch_rwlock_t *rw) in arch_write_unlock() argument
73 __sl_cas(&rw->lock, 0, RW_LOCK_BIAS); in arch_write_unlock()
[all …]
/linux/Documentation/cdrom/
H A Dpacket-writing.rst16 - Grab a new CD-RW disc and format it (assuming CD-RW is hdc, substitute
27 # mount /dev/pktcdvd/dev_name /cdrom -t udf -o rw,noatime
30 Packet writing for DVD-RW media
33 DVD-RW discs can be written to much like CD-RW discs if they are in
37 # dvd+rw-format /dev/hdc
39 You can then use the disc the same way you would use a CD-RW disc::
42 # mount /dev/pktcdvd/dev_name /cdrom -t udf -o rw,noatime
45 Packet writing for DVD+RW media
48 According to the DVD+RW specification, a drive supporting DVD+RW discs
53 # dvd+rw-format /dev/hdc (only needed if the disc has never
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/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h93 #define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7
94 #define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8
110 #define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
111 #define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
112 #define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
113 #define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
114 #define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
115 #define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
116 #define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
117 #define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
[all …]
/linux/drivers/net/ieee802154/
H A Dadf7242.c33 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
35 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
36 #define REG_CCA2 0x106 /* RW CCA mode configuration */
37 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
38 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
[all …]

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