Lines Matching full:rw
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
18 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
19 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
20 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
21 #define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */
22 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
23 #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
24 #define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */
25 #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
26 #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
27 #define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */
30 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
31 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
33 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
35 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
38 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
42 #define E1000_RCTL 0x00100 /* Rx Control - RW */
43 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
44 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
47 #define E1000_TCTL 0x00400 /* Tx Control - RW */
48 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
49 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
50 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
51 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
56 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
58 #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
61 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
63 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
64 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
65 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
66 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
67 #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
68 #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
69 #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
70 #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
71 #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
72 /* Split and Replication Rx Control - RW */
73 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
74 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
114 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
115 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
116 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
117 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
118 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
119 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
120 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
190 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
192 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
193 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
194 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
196 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
197 #define E1000_RA 0x05400 /* Receive Address - RW Array */
198 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
199 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
200 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
202 #define E1000_MANC 0x05820 /* Management Control - RW */
203 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
206 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
207 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
210 #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
223 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
224 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
225 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
226 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
227 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
234 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
239 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
240 #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */