Lines Matching full:rw
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
18 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
19 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
20 #define E1000_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
22 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
24 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
27 #define E1000_RCTL 0x00100 /* RX Control - RW */
28 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
29 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
33 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
35 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
36 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
37 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
38 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
39 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
40 #define E1000_TCTL 0x00400 /* TX Control - RW */
41 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
42 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
43 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
44 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
46 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
51 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
52 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
53 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
54 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
55 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
56 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
57 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
58 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
71 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
72 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
73 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
82 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
84 #define E1000_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
85 #define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
86 #define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
87 #define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
88 #define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
89 #define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
125 /* Split and Replication RX Control - RW */
126 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
179 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
180 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
182 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
183 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
184 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
185 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
186 #define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */
261 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
262 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
276 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
277 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
278 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
279 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
280 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
283 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
284 #define E1000_RA 0x05400 /* Receive Address - RW Array */
285 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
298 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
299 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
300 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
301 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
303 #define E1000_MANC 0x05820 /* Management Control - RW */
304 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
305 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
307 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
315 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
318 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
321 #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */
322 /* MSI-X Allocation Register (_i) - RW */
324 /* Redirection Table - RW Array */
326 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
330 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
334 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
335 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
337 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
338 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
392 #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */