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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2013 - 2024 Intel Corporation */
11 #include "ipu6-buttress.h"
17 #define IPU6_NAME "intel-ipu6"
35 * IPU6 - TGL
36 * IPU6SE - JSL
37 * IPU6EP - ADL/RPL
38 * IPU6EP_MTL - MTL
96 /* The firmware is accessible within the first 2 GiB only in non-secure mode. */
110 * collection capability. CDC FIFO burst collectors have a configurable
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/linux/include/uapi/linux/
H A Dtps6594_pfsm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Userspace ABI for TPS6594 PMIC Pre-configurable Finite State Machine
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
16 * struct pmic_state_opt - PMIC state options
H A Drkisp1-config.h1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */
16 /* Sensor De-gamma */
44 /* Denoise Pre-Filter */
46 /* Denoise Pre-Filter Strength */
129 /* 0-2 for sets 1-3 */
162 * Denoising pre filter
181 * enum rkisp1_cif_isp_version - ISP variants
221 * enum rkisp1_cif_isp_exp_ctrl_autostop - stop modes
231 * enum rkisp1_cif_isp_exp_meas_mode - Exposure measure mode
240 /*---------- PART1: Input Parameters ------------*/
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/linux/drivers/misc/
H A Dtps6594-pfsm.c1 // SPDX-License-Identifier: GPL-2.0
3 * PFSM (Pre-configurable Finite State Machine) driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
35 #define TPS6594_FILE_TO_PFSM(f) container_of((f)->private_data, struct tps6594_pfsm, miscdev)
38 * struct tps6594_pfsm - device private data structure
60 return -EINVAL; in tps6594_pfsm_read()
63 if (count > TPS6594_PMIC_MAX_POS - pos) in tps6594_pfsm_read()
64 count = TPS6594_PMIC_MAX_POS - pos; in tps6594_pfsm_read()
67 ret = regmap_read(pfsm->regmap, pos + i, &val); in tps6594_pfsm_read()
72 return -EFAULT; in tps6594_pfsm_read()
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/linux/drivers/media/dvb-frontends/
H A Ddrxk_hard.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define SCU_RESULT_SIZE -4
25 #define SCU_RESULT_INVPAR -3
26 #define SCU_RESULT_UNKSTD -2
27 #define SCU_RESULT_UNKCMD -1
189 u16 top; /* rf-agc take over point */
190 u16 cut_off_current; /* rf-agc is accelerated if output current
191 is below cut-off current */
197 u16 reference; /* pre SAW reference value, range 0 .. 31 */
198 bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */
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/linux/drivers/clk/
H A Dclk-npcm8xx.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
24 #include <soc/nuvoton/clock-npcm8xx.h>
188 /* configurable pre dividers: */
190 { NPCM8XX_CLKDIV1, 21, 5, "pre_adc", &npcm8xx_muxes[6].hw, CLK_DIVIDER_READ_ONLY, 0, -1 },
194 /* configurable dividers: */
237 val = readl_relaxed(pll->pllcon); in npcm8xx_clk_pll_recalc_rate()
265 return ERR_PTR(-ENOMEM); in npcm8xx_clk_register_pll()
273 pll->pllcon = pllcon; in npcm8xx_clk_register_pll()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
237 provides read-only PLLs, derived from the main crystal clock (which
296 clock. These multi-function devices have two (S2MPS14) or three
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/linux/Documentation/misc-devices/
H A Dtps6594-pfsm.rst1 .. SPDX-License-Identifier: GPL-2.0
12 Strictly speaking, PFSM (Pre-configurable Finite State Machine) is not
23 ---------------
25 - tps6594-q1
26 - tps6593-q1
27 - lp8764-q1
32 drivers/misc/tps6594-pfsm.c
48 required to be always-on, are turned off (low-power).
78 # hexdump -C /dev/pfsm-0-0x48
85 ----------------------
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/linux/Documentation/driver-api/thermal/
H A Dexynos_thermal.rst15 ---------------------------
19 The chip only exposes the measured 8-bit temperature code value
27 Tc = (T - 25) * (TI2 - TI1) / (85 - 25) + TI1
31 Tc = T + TI1 - 25
47 when temperature exceeds pre-defined levels.
48 The maximum number of configurable threshold is five.
65 -----------------------
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
/linux/Documentation/core-api/
H A Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
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/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33 * The input frequency to the timer module in silicon is configurable and
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
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/linux/drivers/gpu/drm/
H A Ddrm_blend.c43 * sub-pixel accuracy, which is scaled up to a pixel-aligned destination
96 * plane-wide opacity, from transparent (0) to opaque (0xffff). It can be
99 * pre-multiplied by the global alpha associated to the plane.
109 * "rotate-<degrees>":
113 * "reflect-<axis>":
117 * reflect-x::
120 * | | -> | |
123 * reflect-y::
126 * | | -> | |
137 * value can also be immutable, to inform userspace about the hard-coded
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/linux/drivers/platform/x86/
H A Dapple-gmux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
123 return inl(gmux_data->iostart + port); in gmux_pio_read32()
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/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * for each configurable rate which is then used to program the clock hardware
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
71 * struct exynos_cpuclk_chip - Chip specific data for CPU clock
83 * struct exynos_cpuclk - information about clock supplied to a CPU core
94 * @chip: chip-specific data for the CPU clock
111 /* ---- Common code --------------------------------------------------------- */
156 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
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/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
28 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
29 * @cfg_phy_cnt: configurable DSP phy data byte count
30 * @stat_id: configurable DSP phy data set ID
34 * @beacon_time_stamp: beacon at on-air rise
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/linux/include/linux/
H A Dlru_cache.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 Copyright (C) 2003-2008, LINBIT Information Technologies GmbH.
8 Copyright (C) 2003-2008, Philipp Reisner <philipp.reisner@linbit.com>.
9 Copyright (C) 2003-2008, Lars Ellenberg <lars.ellenberg@linbit.com>.
24 This header file (and its .c file; kernel-doc of functions see there)
42 we need to resync all regions that have been target of in-flight WRITE IO
48 This is known as "write intent log", and can be implemented as on-disk
53 in-flight WRITE IO, e.g. by only lazily clearing the on-disk write-intent
64 [*] usually as a result of a cluster split-brain and insufficient protection.
68 Having it fine-grained reduces the amount of resync traffic.
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/linux/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
191 * causing h/w - s/w ASID to get out of sync) in local_flush_tlb_mm()
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 Broadcom
11 * OpenGL ES 2.0-compatible 3D engine called V3D, and a highly
12 * configurable display output pipeline that supports HDMI, DSI, DPI,
16 * compute shader-style jobs using the same shader processor as is
27 #include <linux/dma-mapping.h>
41 #include <soc/bcm2835/raspberrypi-firmware.h>
68 int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); in vc4_dumb_fixup_args()
70 if (args->pitch < min_pitch) in vc4_dumb_fixup_args()
71 args->pitch = min_pitch; in vc4_dumb_fixup_args()
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/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
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/linux/Documentation/driver-api/
H A Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
104 1) Set on a pin - the configuration affects all dpll devices pin is
106 2) Set on a pin-dpll tuple - the configuration affects only selected
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/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_shared.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/fsl-diu-fb.h>
36 out_be32(&reset_module_base->rpr, 0x52535445); in mpc512x_restart()
38 out_be32(&reset_module_base->rcr, 0x2); in mpc512x_restart()
47 u8 gamma[0x300]; /* 32-bit aligned! */
48 struct diu_ad ad0; /* 32-bit aligned! */
63 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); in mpc512x_set_pixel_clock()
71 clk_diu = clk_get_sys(np->name, "ipg"); in mpc512x_set_pixel_clock()
85 * determine the acceptable clock range for the monitor (+/- 5%), in mpc512x_set_pixel_clock()
88 pr_debug("DIU pixclock in ps - %u\n", pixclock); in mpc512x_set_pixel_clock()
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/linux/fs/xfs/
H A Dxfs_mount.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2005 Silicon Graphics, Inc.
31 * Error numbers define the errors that are configurable.
45 #define XFS_ERR_RETRY_FOREVER -1
50 * signed 32-bit long is sufficient for a HZ value up to 24855. Making it
51 * signed lets us store the special "-1" value, meaning retry forever.
56 long retry_timeout; /* in jiffies, -1 = infinite */
60 * Per-cpu deferred inode inactivation GC lists.
85 * degenerate case of a pre-rtgroups filesystem, the incore rtgroup
86 * pretends to have a zero-block and zero-blklog rtgroup.
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/linux/drivers/media/i2c/
H A Dmsp3400-driver.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (c) 1997-2001 Gerd Knorr <kraxel@bytesex.org>
9 * AM-Mono
13 * FM-Mono
14 * should work. The stereo modes are backward compatible to FM-mono,
15 * therefore FM-Mono should be always available.
17 * FM-Stereo (B/G, used in germany)
20 * FM-Stereo (satellite)
22 * switch to stereo -- untested)
29 * - better SAT support
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/linux/Documentation/arch/x86/
H A Dtdx.rst1 .. SPDX-License-Identifier: GPL-2.0
18 CPU-attested software module called 'the TDX module' runs inside the new
22 TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to
23 provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs
32 TDX boot-time detection
33 -----------------------
41 ---------------------------------------
59 Besides initializing the TDX module, a per-cpu initialization SEAMCALL
103 ------------------------------------------
110 of memory regions (out of CMRs) as "TDX-usable" memory and pass those
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/linux/arch/arm/kernel/
H A Dtraps.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2009 Russell King
80 frame = ((unsigned long *)frame)[-2] - 4; in dump_backtrace_entry()
104 for (reg = 10, x = 0, p = str; reg >= 0; reg--) { in dump_backtrace_stm()
106 p += sprintf(p, " r%d:%08x", reg, *stack--); in dump_backtrace_stm()
129 return -EFAULT; in verify_stack()
151 str[sizeof(str) - 1] = '\0'; in dump_mem()
179 for (i = -4; i < 1 + !!thumb; i++) { in dump_instr()
289 ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV); in __die()
297 TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), end_of_stack(tsk)); in __die()
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