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/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1800b.dtsi21 interrupt-parent = <&plic>;
38 plic: interrupt-controller@70000000 { label
39 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
H A Dsg2002.dtsi23 interrupt-parent = <&plic>;
40 plic: interrupt-controller@70000000 { label
41 compatible = "sophgo,sg2002-plic", "thead,c900-plic";
H A Dcv1812h.dtsi23 interrupt-parent = <&plic>;
40 plic: interrupt-controller@70000000 { label
41 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
/linux/drivers/irqchip/
H A Dirq-sifive-plic.c6 #define pr_fmt(fmt) "riscv-plic: " fmt
25 * This driver implements a version of the RISC-V PLIC with the actual layout
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
219 .name = "SiFive PLIC",
234 .name = "SiFive PLIC",
527 { .compatible = "sifive,plic-1.0.0" },
531 { .compatible = "thead,c900-plic",
533 { .compatible = "ultrarisc,cp100-plic",
562 pr_err("%pfwP: no PLIC context available\n", fwnode); in plic_parse_nr_irqs_and_contexts()
577 pr_err("%pfwP: no PLIC context available\n", fwnode); in plic_parse_nr_irqs_and_contexts()
[all …]
H A Dirq-sg2042-msi.c298 pr_err("Failed to find the PLIC domain\n"); in sg2042_msi_probe()
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-icicle-kit-fabric.dtsi23 interrupt-parent = <&plic>;
31 interrupt-parent = <&plic>;
41 interrupt-parent = <&plic>;
59 interrupt-parent = <&plic>;
H A Dmpfs-polarberry-fabric.dtsi27 interrupt-parent = <&plic>;
H A Dmpfs-m100pfs-fabric.dtsi27 interrupt-parent = <&plic>;
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml23 (PLIC).
28 tree entry, though external interrupt controllers (like the PLIC, for
30 This means a PLIC interrupt property will typically list the HLICs for all
H A Dsophgo,sg2042-msi.yaml14 PCIe MSI to PLIC interrupts.
62 msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>;
H A Dandestech,plicsw.yaml10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi126 interrupt-parent = <&plic>;
161 plic: interrupt-controller@2000000 { label
162 compatible = "andestech,qilai-plic",
/linux/Documentation/devicetree/bindings/net/
H A Deswin,eic7700-eth.yaml142 interrupt-parent = <&plic>;
168 interrupt-parent = <&plic>;
/linux/Documentation/devicetree/bindings/ata/
H A Deswin,eic7700-ahci.yaml70 interrupt-parent = <&plic>;
/linux/arch/m68k/include/asm/
H A Dm5272sim.h110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
111 #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
/linux/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/
H A Dmicroarch.json62 "BriefDescription": "PLIC arbitration time when the interrupt is not responded",
/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml82 interrupt-parent = <&plic>;
/linux/arch/powerpc/include/asm/
H A Dpaca.h5 * There are some pointers defined that are utilized by PLIC.
70 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
/linux/Documentation/devicetree/bindings/usb/
H A Deswin,eic7700-usb.yaml86 interrupt-parent = <&plic>;
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml78 interrupt-parent = <&plic>;
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
H A Dfu740-c000.dtsi185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi120 compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi357 interrupt-parent = <&plic>;
384 plic: interrupt-controller@c000000 { label
385 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";