xref: /linux/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml (revision 84318277d6334c6981ab326d4acc87c6a6ddc9b8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Eswin EIC7700 SOC Eth Controller
8
9maintainers:
10  - Shuang Liang <liangshuang@eswincomputing.com>
11  - Zhi Li <lizhi2@eswincomputing.com>
12  - Shangjuan Wei <weishangjuan@eswincomputing.com>
13
14description:
15  Platform glue layer implementation for STMMAC Ethernet driver.
16
17select:
18  properties:
19    compatible:
20      contains:
21        enum:
22          - eswin,eic7700-qos-eth
23  required:
24    - compatible
25
26allOf:
27  - $ref: snps,dwmac.yaml#
28
29properties:
30  compatible:
31    items:
32      - const: eswin,eic7700-qos-eth
33      - const: snps,dwmac-5.20
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  interrupt-names:
42    const: macirq
43
44  clocks:
45    items:
46      - description: AXI clock
47      - description: Configuration clock
48      - description: GMAC main clock
49      - description: Tx clock
50
51  clock-names:
52    items:
53      - const: axi
54      - const: cfg
55      - const: stmmaceth
56      - const: tx
57
58  resets:
59    maxItems: 1
60
61  reset-names:
62    items:
63      - const: stmmaceth
64
65  rx-internal-delay-ps:
66    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
67
68  tx-internal-delay-ps:
69    enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
70
71  eswin,hsp-sp-csr:
72    description:
73      HSP CSR is to control and get status of different high-speed peripherals
74      (such as Ethernet, USB, SATA, etc.) via register, which can tune
75      board-level's parameters of PHY, etc.
76    $ref: /schemas/types.yaml#/definitions/phandle-array
77    items:
78      - items:
79          - description: Phandle to HSP(High-Speed Peripheral) device
80          - description: Offset of phy control register for internal
81                         or external clock selection
82          - description: Offset of AXI clock controller Low-Power request
83                         register
84          - description: Offset of register controlling TX/RX clock delay
85
86required:
87  - compatible
88  - reg
89  - clocks
90  - clock-names
91  - interrupts
92  - interrupt-names
93  - phy-mode
94  - resets
95  - reset-names
96  - rx-internal-delay-ps
97  - tx-internal-delay-ps
98  - eswin,hsp-sp-csr
99
100unevaluatedProperties: false
101
102examples:
103  - |
104    ethernet@50400000 {
105        compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
106        reg = <0x50400000 0x10000>;
107        clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
108                <&d0_clock 193>;
109        clock-names = "axi", "cfg", "stmmaceth", "tx";
110        interrupt-parent = <&plic>;
111        interrupts = <61>;
112        interrupt-names = "macirq";
113        phy-mode = "rgmii-id";
114        phy-handle = <&phy0>;
115        resets = <&reset 95>;
116        reset-names = "stmmaceth";
117        rx-internal-delay-ps = <200>;
118        tx-internal-delay-ps = <200>;
119        eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
120        snps,axi-config = <&stmmac_axi_setup>;
121        snps,aal;
122        snps,fixed-burst;
123        snps,tso;
124        stmmac_axi_setup: stmmac-axi-config {
125            snps,blen = <0 0 0 0 16 8 4>;
126            snps,rd_osr_lmt = <2>;
127            snps,wr_osr_lmt = <2>;
128        };
129    };
130