Searched full:mx8qxp (Results 1 – 18 of 18) sorted by relevance
7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
12 model = "TQ-Systems i.MX8QXP TQMa8XQP";
12 model = "TQ-Systems i.MX8QXP TQMa8XQPS";
14 model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx";
14 model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2";
12 model = "Einfochips i.MX8QXP AI_ML";
8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
87 return "i.MX8QXP"; in imx_scu_soc_name()
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
240 MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
138 if (lane->idx == 0) { /* i.MX8QXP */ in imx_hsio_init()158 else /* i.MX8QXP only has PCIEB, idx is 0 */ in imx_hsio_init()
111 This enables the reset controller driver for i.MX8QM/i.MX8QXP
352 MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
237 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
77 * i.MX8QM/i.MX8QXP uses the same map for input and output.80 * clk_map_imx8qxp[0] is for i.MX8QXP asrc081 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1