Home
last modified time | relevance | path

Searched full:mx8qxp (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
H A Dfsl,imx8qxp-ldb.yaml19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8qxp-tqma8xqp.dtsi12 model = "TQ-Systems i.MX8QXP TQMa8XQP";
H A Dimx8qxp-tqma8xqps.dtsi12 model = "TQ-Systems i.MX8QXP TQMa8XQPS";
H A Dimx8qxp-tqma8xqp-mba8xx.dts14 model = "TQ-Systems i.MX8QXP TQMa8XQP on MBa8Xx";
H A Dimx8qxp-tqma8xqps-mb-smarc-2.dts14 model = "TQ-Systems i.MX8QXP TQMa8XQPS on MB-SMARC-2";
H A Dimx8qxp-ai_ml.dts12 model = "Einfochips i.MX8QXP AI_ML";
H A Dimx8qxp-mek.dts12 model = "Freescale i.MX8QXP MEK";
/linux/drivers/firmware/imx/
H A DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
H A Dimx-scu-soc.c87 return "i.MX8QXP"; in imx_scu_soc_name()
/linux/Documentation/devicetree/bindings/phy/
H A Dmixel,mipi-dsi-phy.yaml17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
/linux/Documentation/devicetree/bindings/clock/
H A Dimx8qxp-lpcg.yaml7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx8qxp.c240 MODULE_DESCRIPTION("NXP i.MX8QXP pinctrl driver");
/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c138 if (lane->idx == 0) { /* i.MX8QXP */ in imx_hsio_init()
158 else /* i.MX8QXP only has PCIEB, idx is 0 */ in imx_hsio_init()
/linux/Documentation/devicetree/bindings/arm/
H A Dfsl.yaml1353 - description: i.MX8QXP based Boards
1356 - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
1357 - fsl,imx8qxp-mek # i.MX8QXP MEK Board
1358 - fsl,imx8qxp-mek-wcpu # i.MX8QXP MEK WCPU Board
1367 - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
1392 - const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
/linux/drivers/clk/imx/
H A Dclk-imx8qxp.c352 MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
/linux/drivers/reset/
H A DKconfig122 This enables the reset controller driver for i.MX8QM/i.MX8QXP
/linux/drivers/remoteproc/
H A Dimx_dsp_rproc.c1017 * On i.MX8QM and i.MX8QXP there is multiple power domains
1076 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
1354 /* Specific configuration for i.MX8QXP */
/linux/sound/soc/fsl/
H A Dfsl_mqs.c237 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
H A Dfsl_asrc.c77 * i.MX8QM/i.MX8QXP uses the same map for input and output.
80 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
81 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1