Home
last modified time | relevance | path

Searched full:mx8qm (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
H A Dfsl,imx8qxp-pixel-link.yaml7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
H A Dfsl,imx8qxp-pixel-combiner.yaml7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
H A Dfsl,imx8qm-hsio.yaml7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
50 Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
53 | | i.MX8QM |
/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml67 Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
71 - description: phandle to the first lane PHY of i.MX8QM.
72 - description: phandle to the second lane PHY of i.MX8QM.
/linux/drivers/firmware/imx/
H A DKconfig8 DSP exists on some i.MX8 processors (e.g i.MX8QM, i.MX8QXP).
20 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
H A Dimx-scu-soc.c85 return "i.MX8QM"; in imx_scu_soc_name()
/linux/drivers/net/can/flexcan/
H A Dflexcan.h30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c143 * On i.MX8QM, only second or third lane can be in imx_hsio_init()
164 /* On i.MX8QM, only the third lane can be bound to SATA */ in imx_hsio_init()
/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx8qm.c333 MODULE_DESCRIPTION("NXP i.MX8QM pinctrl driver");
/linux/drivers/reset/
H A DKconfig111 This enables the reset controller driver for i.MX8QM/i.MX8QXP
/linux/sound/soc/fsl/
H A Dfsl_mqs.c237 * But in i.MX8QM/i.MX8QXP the control register is moved in fsl_mqs_probe()
H A Dfsl_asrc.c77 * i.MX8QM/i.MX8QXP uses the same map for input and output.
78 * clk_map_imx8qm[0] is for i.MX8QM asrc0
79 * clk_map_imx8qm[1] is for i.MX8QM asrc1
/linux/drivers/ata/
H A Dahci_imx.c424 * Since "REXT" pin is only present for first lane of i.MX8QM in imx8_sata_enable()
/linux/drivers/tty/serial/
H A Dfsl_lpuart.c1595 * Another bug is i.MX8QM LPUART may have an additional break character in lpuart32_break_ctl()