Searched full:mx7ulp (Results 1 – 14 of 14) sorted by relevance
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller13 i.MX7ULP Clock functions are under joint control of the System38 i.MX7ULP clock IDs of each module.
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller13 i.MX7ULP Clock functions are under joint control of the System35 i.MX7ULP clock IDs of each module.
7 title: Freescale i.MX7ULP IOMUX Controller47 Please refer to i.MX7ULP Reference Manual for detailed
7 title: Freescale i.MX7ULP System Integration Module
11 model = "Embedded Artists i.MX7ULP COM";
13 model = "NXP i.MX7ULP EVK";
80 DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
209 bool "i.MX7ULP support"
17 i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93/5 SoCs.
238 .identity = "i.MX7ULP watchdog timer",429 MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
123 soc_id = "i.MX7ULP"; in imx_soc_device_init()
3 // Freescale i.MX7ULP LPSPI driver38 /* i.MX7ULP LPSPI registers */
490 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. in fsl_edma2_irq_init()493 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. in fsl_edma2_irq_init()
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x3183 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers in lpuart_console_fixup()