1a505e52aSAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2a505e52aSAnson Huang%YAML 1.2 3a505e52aSAnson Huang--- 4a505e52aSAnson Huang$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml# 5a505e52aSAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6a505e52aSAnson Huang 7a505e52aSAnson Huangtitle: Freescale i.MX7ULP System Integration Module 8a505e52aSAnson Huang 9a505e52aSAnson Huangmaintainers: 10*499f5e3cSKrzysztof Kozlowski - Shawn Guo <shawnguo@kernel.org> 11*499f5e3cSKrzysztof Kozlowski - Sascha Hauer <s.hauer@pengutronix.de> 12*499f5e3cSKrzysztof Kozlowski - Fabio Estevam <festevam@gmail.com> 13a505e52aSAnson Huang 14a505e52aSAnson Huangdescription: | 15a505e52aSAnson Huang The system integration module (SIM) provides system control and chip configuration 16a505e52aSAnson Huang registers. In this module, chip revision information is located in JTAG ID register, 17a505e52aSAnson Huang and a set of registers have been made available in DGO domain for SW use, with the 18a505e52aSAnson Huang objective to maintain its value between system resets. 19a505e52aSAnson Huang 20a505e52aSAnson Huangproperties: 21a505e52aSAnson Huang compatible: 22a505e52aSAnson Huang items: 23a505e52aSAnson Huang - const: fsl,imx7ulp-sim 24a505e52aSAnson Huang - const: syscon 25a505e52aSAnson Huang 26a505e52aSAnson Huang reg: 27a505e52aSAnson Huang maxItems: 1 28a505e52aSAnson Huang 29a505e52aSAnson Huangrequired: 30a505e52aSAnson Huang - compatible 31a505e52aSAnson Huang - reg 32a505e52aSAnson Huang 33a505e52aSAnson HuangadditionalProperties: false 34a505e52aSAnson Huang 35a505e52aSAnson Huangexamples: 36a505e52aSAnson Huang - | 37a505e52aSAnson Huang sim@410a3000 { 38a505e52aSAnson Huang compatible = "fsl,imx7ulp-sim", "syscon"; 39a505e52aSAnson Huang reg = <0x410a3000 0x1000>; 40a505e52aSAnson Huang }; 41