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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8196-clock.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
7 title: MediaTek Functional Clock Controller for MT8196
27 - mediatek,mt8196-imp-iic-wrap-c
28 - mediatek,mt8196-imp-iic-wrap-e
29 - mediatek,mt8196-imp-iic-wrap-n
30 - mediatek,mt8196-imp-iic-wrap-w
31 - mediatek,mt8196-mdpsys0
32 - mediatek,mt8196-mdpsys1
33 - mediatek,mt8196-pericfg-ao
34 - mediatek,mt8196-pextp0cfg-ao
[all …]
H A Dmediatek,mt8196-sys-clock.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
7 title: MediaTek System Clock Controller for MT8196
30 - mediatek,mt8196-apmixedsys
31 - mediatek,mt8196-armpll-b-pll-ctrl
32 - mediatek,mt8196-armpll-bl-pll-ctrl
33 - mediatek,mt8196-armpll-ll-pll-ctrl
34 - mediatek,mt8196-apmixedsys-gp2
35 - mediatek,mt8196-ccipll-pll-ctrl
36 - mediatek,mt8196-mfgpll-pll-ctrl
37 - mediatek,mt8196-mfgpll-sc0-pll-ctrl
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8196-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
7 title: MediaTek MT8196 Pin Controller
14 The MediaTek's MT8196 Pin controller is used to control SoC pins.
18 const: mediatek,mt8196-pinctrl
114 defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
124 description: mt8196 pull down PUPD/R0/R1 type define value.
126 description: mt8196 pull down RSEL type si unit value(ohm).
133 "MTK_PUPD_SET_R1R0_11" define in mt8196.
137 value(ohm) "75000" & "5000" in mt8196.
143 description: mt8196 pull up PUPD/R0/R1 type define value.
[all …]
/linux/drivers/clk/mediatek/
H A DMakefile154 obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
155 clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
156 clk-mt8196-peri_ao.o
157 obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
158 obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
159 obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
160 obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
161 obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.…
162 clk-mt8196-ovl0.o clk-mt8196-ovl1.o
163 obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
[all …]
H A DKconfig1016 tristate "Clock driver for MediaTek MT8196"
1022 This driver supports MediaTek MT8196 basic clocks.
1025 tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
1029 This driver supports MediaTek MT8196 i2c clocks.
1032 tristate "Clock driver for MediaTek MT8196 mcusys"
1036 This driver supports MediaTek MT8196 mcusys clocks.
1039 tristate "Clock driver for MediaTek MT8196 mdpsys"
1043 This driver supports MediaTek MT8196 mdpsys clocks.
1046 tristate "Clock driver for MediaTek MT8196 mfgcfg"
1050 This driver supports MediaTek MT8196 mfgcfg clocks.
[all …]
H A Dclk-mt8196-imp_iic_wrap.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
99 { .compatible = "mediatek,mt8196-imp-iic-wrap-c", .data = &impc_mcd },
100 { .compatible = "mediatek,mt8196-imp-iic-wrap-e", .data = &impe_mcd },
101 { .compatible = "mediatek,mt8196-imp-iic-wrap-n", .data = &impn_mcd },
102 { .compatible = "mediatek,mt8196-imp-iic-wrap-w", .data = &impw_mcd },
111 .name = "clk-mt8196-imp_iic_wrap",
117 MODULE_DESCRIPTION("MediaTek MT8196 I2C Wrapper clocks driver");
H A Dclk-mt8196-pextp.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
9 #include <dt-bindings/reset/mediatek,mt8196-resets.h>
114 { .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd },
115 { .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd },
124 .name = "clk-mt8196-pextp",
130 MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver");
H A Dclk-mt8196-ufs_ao.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
9 #include <dt-bindings/reset/mediatek,mt8196-resets.h>
92 { .compatible = "mediatek,mt8196-ufscfg-ao", .data = &ufsao_mcd },
101 .name = "clk-mt8196-ufs-ao",
107 MODULE_DESCRIPTION("MediaTek MT8196 ufs_ao clocks driver");
H A Dclk-mt8196-vdisp_ao.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
64 { .compatible = "mediatek,mt8196-vdisp-ao", .data = &mm_v_mcd },
73 .name = "clk-mt8196-vdisp-ao",
79 MODULE_DESCRIPTION("MediaTek MT8196 vdisp_ao clocks driver");
H A Dclk-mt8196-venc.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
218 { .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
219 { .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
220 { .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
229 .name = "clk-mt8196-venc",
235 MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
H A Dclk-mt8196-vdec.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
236 { .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd },
237 { .compatible = "mediatek,mt8196-vdecsys-soc", .data = &vde1_mcd },
246 .name = "clk-mt8196-vdec",
252 MODULE_DESCRIPTION("MediaTek MT8196 Video Decoders clocks driver");
H A Dclk-mt8196-peri_ao.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
126 { .compatible = "mediatek,mt8196-pericfg-ao", .data = &peri_ao_mcd },
135 .name = "clk-mt8196-peri-ao",
140 MODULE_DESCRIPTION("MediaTek MT8196 pericfg_ao clock controller driver");
H A Dclk-mt8196-mdpsys.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
169 { .compatible = "mediatek,mt8196-mdpsys0", .data = &mdp_mcd },
170 { .compatible = "mediatek,mt8196-mdpsys1", .data = &mdp1_mcd },
179 .name = "clk-mt8196-mdpsys",
185 MODULE_DESCRIPTION("MediaTek MT8196 Multimedia Data Path clocks driver");
H A Dclk-mt8196-ovl1.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
138 { .name = "clk-mt8196-ovl1", .driver_data = (kernel_ulong_t)&ovl1_mcd },
147 .name = "clk-mt8196-ovl1",
153 MODULE_DESCRIPTION("MediaTek MT8196 ovl1 clocks driver");
H A Dclk-mt8196-ovl0.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
138 { .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
147 .name = "clk-mt8196-ovl0",
153 MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
H A Dclk-mt8196-disp0.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
154 { .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
163 .name = "clk-mt8196-disp0",
169 MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver");
H A Dclk-mt8196-disp1.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
154 { .name = "clk-mt8196-disp1", .driver_data = (kernel_ulong_t)&mm1_mcd },
163 .name = "clk-mt8196-disp1",
169 MODULE_DESCRIPTION("MediaTek MT8196 disp1 clocks driver");
H A Dclk-mt8196-topckgen2.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
552 { .compatible = "mediatek,mt8196-topckgen-gp2", .data = &topck_desc },
561 .name = "clk-mt8196-topck2",
566 MODULE_DESCRIPTION("MediaTek MT8196 GP2 top clock generators driver");
H A Dclk-mt8196-vlpckgen.c8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
708 { .compatible = "mediatek,mt8196-vlpckgen" },
717 .name = "clk-mt8196-vlpck",
722 MODULE_DESCRIPTION("MediaTek MT8196 VLP clock generator driver");
/linux/Documentation/devicetree/bindings/thermal/
H A Dmediatek,lvts-thermal.yaml30 - mediatek,mt8196-lvts-ap
31 - mediatek,mt8196-lvts-mcu
103 - mediatek,mt8196-lvts-ap
104 - mediatek,mt8196-lvts-mcu
/linux/drivers/interconnect/mediatek/
H A Dmt8196.c12 #include <dt-bindings/interconnect/mediatek,mt8196.h>
363 { .compatible = "mediatek,mt8196-emi", .data = &mt8196_emi_icc },
370 .name = "emi-icc-mt8196",
381 MODULE_DESCRIPTION("MediaTek MT8196 EMI ICC driver");
/linux/drivers/pinctrl/mediatek/
H A DKconfig294 tristate "MediaTek MT8196 pin control"
301 on MediaTek MT8196 SoC.
/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml29 - mediatek,mt8196-mmc
197 - mediatek,mt8196-mmc
245 - mediatek,mt8196-mmc
/linux/Documentation/devicetree/bindings/regulator/
H A Dmediatek,mt6873-dvfsrc-regulator.yaml24 - mediatek,mt8196-dvfsrc-regulator
/linux/drivers/phy/mediatek/
H A DMakefile24 phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8196.o

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