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/linux/drivers/bus/
H A D	omap_l3_noc.c	3 * OMAP L3 Interconnect error handling driver 23 * @l3: pointer to l3 struct 35 * 1) Custom errors in L3 : 37 * 2) Standard L3 error: 39 * L3 tries to access target while it is idle 50 static int l3_handle_target(struct omap_l3 l3, void __iomem base, in l3_handle_target() argument 114 l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask); in l3_handle_target() 116 for (k = 0, master = l3->l3_masters; k < l3->num_masters; in l3_handle_target() 134 "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n", in l3_handle_target() 135 dev_name(l3->dev), in l3_handle_target() [all …]
H A D	omap_l3_smx.c	3 * OMAP3XXX L3 Interconnect Driver 129 * @l3: struct omap3_l3 * 139 static irqreturn_t omap3_l3_block_irq(struct omap3_l3 l3, in omap3_l3_block_irq() argument 158 struct omap3_l3 l3 = _l3; in omap3_l3_app_irq() local 167 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; in omap3_l3_app_irq() 169 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); in omap3_l3_app_irq() 171 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); in omap3_l3_app_irq() 176 base = l3->rt + omap3_l3_bases[int_type][err_source]; in omap3_l3_app_irq() 180 ret \|= omap3_l3_block_irq(l3, error, error_addr); in omap3_l3_app_irq() 205 .compatible = "ti,omap3-l3-smx", [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	memory.json	42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 75 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 81 …dified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDI… 86 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 92 …dified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDI… 108 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 114 … fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDI… [all …]
H A D	cache.json	67 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, … 76 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, … 169 …"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a s… 175 …"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a … 224 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 230 …"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache. Available P… 312 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 318 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache. Available PDIST co… 323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	memory.json	42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 75 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 81 …dified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDI… 86 …": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 92 …dified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDI… 108 …d instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 114 … fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDI… [all …]
H A D	cache.json	67 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, … 76 …struction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, … 169 …"BriefDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a s… 175 …"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache, in which a … 224 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", 230 …"PublicDescription": "Counts the number of load uops retired that hit in the L3 cache. Available P… 312 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 318 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache. Available PDIST co… 323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state", 8 … "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 13 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", 18 "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", 23 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", 28 "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", 33 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", 38 … "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 43 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", 48 … "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du… 160 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t… 165 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … 170 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L3 due t… 175 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … 180 …t dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss… 185 …t dispatch conflicts with data NOT in the MEPF state from the local core's L3 due to a demand miss… 190 …th data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss… 195 …th data in the MEPF state without dispatch conflicts from the local core's L3 due to a demand miss… 200 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L3 due to a … [all …]
/linux/arch/sparc/kernel/
H A D	head_64.S	`175 mov 1, %l3 176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 199 mov 4, %l3 200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 201 mov 1, %l3 202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 206 mov 64, %l3 207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size 214 mov (1b - prom_boot_mapped_pc), %l3 [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand … 66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o… 71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)", 77 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load… 78 …ssor's data cache was reloaded from a location other than the local core's L3 due to either only d… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… [all …]
H A D	metrics.json	207 …escription": "Cycles stalled by GCT empty due to Icache misses that resolve in the local L2 or L3", 255 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t… 261 "BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3", 267 …"BriefDescription": "Cycles stalled by D-Cache Misses that resolved in the local L2 or L3, where t… 456 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Modified) per Inst", 462 "BriefDescription": "% of DL1 Reloads from Distant L2 or L3 (Shared) per Inst", 522 "BriefDescription": "% of DL1 reloads from Private L3 M state, other core per Inst", 528 "BriefDescription": "% of DL1 reloads from Private L3 S tate, other core per Inst", 534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen… 540 "BriefDescription": "% of DL1 reloads from L3 per Inst", [all …]
H A D	marked.json	35 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 41 …ation in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node … 47 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 53 …uration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node … 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … 161 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load… 167 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load… 173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load", 179 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co… 185 …"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due … [all …]
H A D	frontend.json	89 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 90 …uction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node … 95 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 96 …truction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node … 149 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an… 150 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to e… 156 "PublicDescription": "Inst from L3 miss" 161 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction… 162 …Instruction cache was reloaded from a location other than the local core's L3 due to either an ins… 167 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with disp… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	memory.json	3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 204 "BriefDescription": "Demand Data Read requests who miss L3 cache", 208 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 213 …"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the sup… 222 … "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ … 230 …"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the su… 239 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 249 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified dat… 259 …"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared … [all …]
H A D	cache.json	59 …n": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed t… 63 …n": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed t… 68 …"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with t… 72 …ion": "Counts number of cache lines that are allocated and written back to L3 with the intention t… 133 …either be written back to L3 or directly written to memory and not allocated in L3. Clean lines m… 137 …either be written back to L3 or directly written to memory and not allocated in L3. Clean lines m… 203 … "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches", 266 …"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches t… 270 …"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software pref… 275 …"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches t… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A D	l3-cache.json	5 "BriefDescription": "L3 cache misses.", 12 "BriefDescription": "L3 cache hits.", 19 "BriefDescription": "L3 cache requests for all coherent accesses.", 26 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in t… 37 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from DRAM in a… 48 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of … 59 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from cache of … 70 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from extension… 81 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from extension… 92 …"BriefDescription": "Average sampled latency for L3 requests where data is returned from all types… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	uncore-cache.json	3 … "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", 12 "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", 21 "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", 30 "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", 39 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-s… 48 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.… 57 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.… 66 …"BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-sta… 75 … "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", 84 "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", [all …]
/linux/arch/x86/kernel/cpu/
H A D	amd_cache_disable.c	3 * AMD L3 cache_disable_{0,1} sysfs handling 17 * L3 cache descriptors 21 struct amd_l3_cache *l3 = &nb->l3_cache; in amd_calc_l3_indices() local 28 l3->subcaches[0] = sc0 = !(val & BIT(0)); in amd_calc_l3_indices() 29 l3->subcaches[1] = sc1 = !(val & BIT(4)); in amd_calc_l3_indices() 32 l3->subcaches[0] = sc0 += !(val & BIT(1)); in amd_calc_l3_indices() 33 l3->subcaches[1] = sc1 += !(val & BIT(5)); in amd_calc_l3_indices() 36 l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9)); in amd_calc_l3_indices() 37 l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13)); in amd_calc_l3_indices() 39 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1; in amd_calc_l3_indices() [all …]
/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A D	cache.json	73 …red by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", 240 …ption": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)… 244 …L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs)… 329 …"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hit… 334 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s… 339 …iefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 344 …iption": "Counts retired load instructions whose data sources were HitM responses from shared L3.", 349 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 354 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… 359 …"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops r… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelake/
H A D	cache.json	73 …red by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", 240 …ption": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)… 244 …L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs)… 329 …"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hit… 334 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s… 339 …iefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 344 …iption": "Counts retired load instructions whose data sources were HitM responses from shared L3.", 349 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop… 354 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros… 359 …"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops r… [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	other.json	35 "BriefDescription": "L3 initiated LCO received retry on port 2 (can try 4 times)" 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 50 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 120 …"BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to … 160 "BriefDescription": "L3 PF from Off chip memory" 190 …"BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modifie… 205 …uration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due… 235 … "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated" 245 "BriefDescription": "L3 PF sent with nodal scope port 1, counts even retried requests" 260 "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" [all …]
H A D	marked.json	10 …ory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The sour… 20 …ble Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due… 50 …Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This imp… 70 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 85 …Instruction cache was reloaded from a location other than the local core's L3 due to a instruction… 95 …try was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due… 100 …Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due… 110 … "Duration in cycles to reload from a location other than the local core's L3 due to a marked load" 180 …ocessor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due… 185 …essor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due… [all …]

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