Lines Matching full:l3
5 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
6 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node …
11 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
12 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node …
65 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand …
66 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either o…
71 "BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
77 …ssor's data cache was reloaded from a location other than the local core's L3 due to a demand load…
78 …ssor's data cache was reloaded from a location other than the local core's L3 due to either only d…
83 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch co…
84 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch c…
89 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch…
90 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatc…
95 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict…
96 …"PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflic…
107 …a cache was reloaded either shared or modified data from another core's L2/L3 on a different chip …
108 …a cache was reloaded either shared or modified data from another core's L2/L3 on a different chip …
113 …a cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due…
114 …a cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due…
119 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or …
120 …s data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or …
125 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or …
126 …r's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or …
137 … Entry was loaded into the TLB from a location other than the local core's L3 due to a data side r…