| /freebsd/sys/powerpc/powermac/ |
| H A D | cpcht.c | 85 int *irq);
87 int irq);
89 int irq, uint64_t *addr, uint32_t *data);
201 mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF); in cpcht_attach()
220 int i, nirq, irq; in cpcht_configure_htbridge() local
260 /* Find the HT IRQ capabilities */ in cpcht_configure_htbridge()
269 /* Ask for the IRQ count */ in cpcht_configure_htbridge()
279 irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4); in cpcht_configure_htbridge()
285 irq | HTAPIC_MASK, 4); in cpcht_configure_htbridge()
286 irq = (irq >> 16) & 0xff; in cpcht_configure_htbridge()
[all …]
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| H A D | hrowpic.c | 177 hrowpic_toggle_irq(struct hrowpic_softc *sc, int irq, int enable) in hrowpic_toggle_irq() argument
182 KASSERT((irq > 0) && (irq <= HROWPIC_IRQMAX), ("en irq out of range")); in hrowpic_toggle_irq()
187 if (irq == HROWPIC_IRQMAX) in hrowpic_toggle_irq()
191 * Calculate prim/sec register bank for the IRQ, update soft copy, in hrowpic_toggle_irq()
192 * and enable the IRQ as an interrupt source in hrowpic_toggle_irq()
194 roffset = HPIC_INT_TO_BANK(irq); in hrowpic_toggle_irq()
195 rbit = HPIC_INT_TO_REGBIT(irq); in hrowpic_toggle_irq()
215 u_int irq; in hrowpic_dispatch() local
225 irq = 0; in hrowpic_dispatch()
226 while (irq < HROWPIC_IRQMAX) { in hrowpic_dispatch()
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| /freebsd/sys/arm/allwinner/a10/ |
| H A D | a10_intc.c | 96 u_int irq; member
114 a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq) in a10_intr_eoi() argument
117 if (irq != SW_INT_IRQNO_ENMI) in a10_intr_eoi()
126 a10_intr_unmask(struct a10_aintc_softc *sc, u_int irq) in a10_intr_unmask() argument
130 bit = (irq % 32); in a10_intr_unmask()
131 block = (irq / 32); in a10_intr_unmask()
145 a10_intr_mask(struct a10_aintc_softc *sc, u_int irq) in a10_intr_mask() argument
149 bit = (irq % 32); in a10_intr_mask()
150 block = (irq / 32); in a10_intr_mask()
186 u_int irq; in a10_intr() local
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| /freebsd/sys/i386/pci/ |
| H A D | pci_pir.c | 83 int irq);
95 static int pci_pir_valid_irq(struct pci_link *pci_link, int irq);
195 * Check to see if a possible IRQ setting is valid.
198 pci_pir_valid_irq(struct pci_link *pci_link, int irq) in pci_pir_valid_irq() argument
201 if (!PCI_INTERRUPT_VALID(irq)) in pci_pir_valid_irq()
203 return (pci_link->pl_irqmask & (1 << irq)); in pci_pir_valid_irq()
304 * Try to initialize IRQ based on this device's IRQ.
311 uint8_t irq, pin; in pci_pir_initial_irqs() local
315 irq = pci_pir_search_irq(entry->pe_bus, entry->pe_device, pin); in pci_pir_initial_irqs()
316 if (irq == PCI_INVALID_IRQ || irq == pci_link->pl_irq) in pci_pir_initial_irqs()
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| /freebsd/usr.sbin/bhyve/amd64/ |
| H A D | pci_irq.c | 59 #define IRQ_PERMITTED(irq) (((1U << (irq)) & PERMITTED_IRQS) != 0) argument
61 /* IRQ count to disable an IRQ. */
77 * Returns true if this pin is enabled with a valid IRQ. Setting the
78 * register to a reserved IRQ causes interrupts to not be asserted as
117 pci_irq_reserve(int irq) in pci_irq_reserve() argument
120 assert(irq >= 0 && irq < NIRQ_COUNTS); in pci_irq_reserve()
122 assert(irq_counts[irq] == 0 || irq_counts[irq] == IRQ_DISABLED); in pci_irq_reserve()
123 irq_counts[irq] = IRQ_DISABLED; in pci_irq_reserve()
127 pci_irq_use(int irq) in pci_irq_use() argument
130 assert(irq >= 0 && irq < NIRQ_COUNTS); in pci_irq_use()
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| /freebsd/sys/compat/linuxkpi/common/src/ |
| H A D | linux_interrupt.c | 47 unsigned int irq; member
51 lkpi_irq_rid(struct device *dev, unsigned int irq) in lkpi_irq_rid() argument
54 if (irq >= dev->irq_start && irq < dev->irq_end) in lkpi_irq_rid()
55 return (irq - dev->irq_start + 1); in lkpi_irq_rid()
61 lkpi_irq_ent(struct device *dev, unsigned int irq) in lkpi_irq_ent() argument
66 if (irqe->irq == irq) in lkpi_irq_ent()
81 if (irqe->handler(irqe->irq, irqe->arg) == IRQ_WAKE_THREAD && in lkpi_irq_handler()
84 irqe->thread_handler(irqe->irq, irqe->arg); in lkpi_irq_handler()
113 lkpi_request_irq(struct device *xdev, unsigned int irq, in lkpi_request_irq() argument
124 dev = lkpi_pci_find_irq_dev(irq); in lkpi_request_irq()
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| /freebsd/sys/arm64/vmm/io/ |
| H A D | vgic_v3.c | 100 uint32_t irq; member
467 struct vgic_v3_irq *irq; in vgic_v3_cpuinit() local
478 irq = &vgic_cpu->private_irqs[irqid]; in vgic_v3_cpuinit()
480 mtx_init(&irq->irq_spinmtx, "VGIC IRQ spinlock", NULL, in vgic_v3_cpuinit()
482 irq->irq = irqid; in vgic_v3_cpuinit()
483 irq->mpidr = hypctx->vmpidr_el2 & GICD_AFF; in vgic_v3_cpuinit()
484 irq->target_vcpu = vcpu_vcpuid(hypctx->vcpu); in vgic_v3_cpuinit()
485 MPASS(irq->target_vcpu >= 0); in vgic_v3_cpuinit()
489 irq->enabled = true; in vgic_v3_cpuinit()
490 irq->config = VGIC_CONFIG_EDGE; in vgic_v3_cpuinit()
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| /freebsd/sys/arm/arm/ |
| H A D | gic.c | 118 #define GI_FLAG_MSI_USED (1 << 2) /* This irq is already allocated */
131 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) argument
165 gic_irq_unmask(struct arm_gic_softc *sc, u_int irq) in gic_irq_unmask() argument
168 gic_d_write_4(sc, GICD_ISENABLER(irq), GICD_I_MASK(irq)); in gic_irq_unmask()
172 gic_irq_mask(struct arm_gic_softc *sc, u_int irq) in gic_irq_mask() argument
175 gic_d_write_4(sc, GICD_ICENABLER(irq), GICD_I_MASK(irq)); in gic_irq_mask()
206 u_int irq, cpu; in arm_gic_init_secondary() local
213 for (irq = 0; irq < sc->nirqs; irq += 4) in arm_gic_init_secondary()
214 gic_d_write_4(sc, GICD_IPRIORITYR(irq), 0); in arm_gic_init_secondary()
217 for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) { in arm_gic_init_secondary()
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| /freebsd/sys/arm64/apple/ |
| H A D | apple_aic.c | 78 #define AIC_TARGET_CPU(irq) (0x3000 + (irq) * 4) argument
79 #define AIC_SW_SET(irq) (0x4000 + (((irq) >> 5) * 4)) argument
80 #define AIC_SW_CLEAR(irq) (0x4080 + (((irq) >> 5) * 4)) argument
81 #define AIC_MASK_SET(irq) (0x4100 + (((irq) >> 5) * 4)) argument
82 #define AIC_MASK_CLEAR(irq) (0x4180 + (((irq) >> 5) * 4)) argument
83 #define AIC_IRQ_MASK(irq) (1u << ((irq) & 0x1f)) argument
243 device_printf(dev, "Unable to register irq %u:%u\n", in apple_aic_attach()
286 struct intr_map_data_fdt *data, u_int *irq, enum apple_aic_irq_type *typep, in apple_aic_map_intr_fdt() argument
297 * 0 = IRQ in apple_aic_map_intr_fdt()
315 *irq = data->cells[1]; in apple_aic_map_intr_fdt()
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| /freebsd/sys/compat/linuxkpi/common/include/linux/ |
| H A D | interrupt.h | 59 request_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, in request_irq() argument
63 return (lkpi_request_irq(NULL, irq, handler, NULL, flags, name, arg)); in request_irq()
67 request_threaded_irq(int irq, irq_handler_t handler, in request_threaded_irq() argument
72 return (lkpi_request_irq(NULL, irq, handler, thread_handler, in request_threaded_irq()
77 devm_request_irq(struct device *dev, int irq, in devm_request_irq() argument
81 return (lkpi_request_irq(dev, irq, handler, NULL, flags, name, arg)); in devm_request_irq()
85 devm_request_threaded_irq(struct device *dev, int irq, in devm_request_threaded_irq() argument
90 return (lkpi_request_irq(dev, irq, handler, thread_handler, in devm_request_threaded_irq()
95 enable_irq(unsigned int irq) in enable_irq() argument
97 return (lkpi_enable_irq(irq)); in enable_irq()
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| /freebsd/sys/arm/ti/ |
| H A D | aintc.c | 106 ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq) in ti_aintc_irq_mask() argument
109 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); in ti_aintc_irq_mask()
113 ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq) in ti_aintc_irq_unmask() argument
116 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); in ti_aintc_irq_unmask()
122 uint32_t irq; in ti_aintc_intr() local
126 irq = aintc_read_4(sc, INTC_SIR_IRQ); in ti_aintc_intr()
127 if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) { in ti_aintc_intr()
129 "Spurious interrupt detected (0x%08x)\n", irq); in ti_aintc_intr()
135 irq &= INTC_SIR_ACTIVE_MASK; in ti_aintc_intr()
136 if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc, in ti_aintc_intr()
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| H A D | ti_pruss.c | 221 struct ti_pruss_irqsc* irq; in ti_pruss_irq_read() local
227 irq = cdev->si_drv1; in ti_pruss_irq_read()
236 mtx_lock(&irq->sc_mtx); in ti_pruss_irq_read()
238 if (irq->tstamps.ctl.cnt - priv->cnt > TI_TS_ARRAY) in ti_pruss_irq_read()
240 priv->cnt = irq->tstamps.ctl.cnt; in ti_pruss_irq_read()
241 priv->idx = irq->tstamps.ctl.idx; in ti_pruss_irq_read()
242 mtx_unlock(&irq->sc_mtx); in ti_pruss_irq_read()
248 level = irq->tstamps.ctl.idx - idx; in ti_pruss_irq_read()
254 mtx_unlock(&irq->sc_mtx); in ti_pruss_irq_read()
258 error = msleep(irq, &irq->sc_mtx, PCATCH | PDROP, in ti_pruss_irq_read()
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| /freebsd/sys/dev/gve/ |
| H A D | gve_utils.c | 226 struct gve_irq *irq; in gve_free_irqs() local
233 device_printf(priv->dev, "No irq table, nothing to free\n"); in gve_free_irqs()
240 irq = &priv->irq_tbl[i]; in gve_free_irqs()
241 if (irq->res == NULL) in gve_free_irqs()
244 rid = rman_get_rid(irq->res); in gve_free_irqs()
246 rc = bus_teardown_intr(priv->dev, irq->res, irq->cookie); in gve_free_irqs()
248 device_printf(priv->dev, "Failed to teardown irq num %d\n", in gve_free_irqs()
252 rid, irq->res); in gve_free_irqs()
254 device_printf(priv->dev, "Failed to release irq num %d\n", in gve_free_irqs()
257 irq->res = NULL; in gve_free_irqs()
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| /freebsd/sys/arm64/arm64/ |
| H A D | gic_v3.c | 186 #define GI_FLAG_MSI_USED (1 << 2) /* This irq is already allocated */
306 u_int irq; in gic_v3_attach() local
359 for (irq = 0; irq < sc->gic_nirqs; irq++) { in gic_v3_attach()
362 sc->gic_irqs[irq].gi_irq = irq; in gic_v3_attach()
363 sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM; in gic_v3_attach()
364 sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM; in gic_v3_attach()
366 isrc = &sc->gic_irqs[irq] in gic_v3_attach()
663 u_int irq; gic_map_fdt() local
767 u_int irq; do_gic_v3_map_intr() local
831 u_int irq; gic_v3_map_intr() local
853 u_int irq = gi->gi_irq; gic_v3_setup_intr_periph() local
901 u_int irq; gic_v3_setup_intr() local
966 u_int irq; gic_v3_disable_intr() local
992 u_int irq = gi->gi_irq; gic_v3_enable_intr_periph() local
1006 u_int irq; gic_v3_enable_intr() local
1103 u_int cpu, irq; gic_v3_init_secondary() local
1152 uint64_t aff, val, irq; gic_v3_ipi_send() local
1519 int i, irq, end_irq; gic_v3_gic_alloc_msi() local
1607 int irq; gic_v3_gic_alloc_msix() local
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_gpio.c | 118 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */
181 u_int irq; in gpio_pic_map_fdt() local
201 irq = daf->cells[0]; in gpio_pic_map_fdt()
202 if (irq >= sc->gpio_npins) { in gpio_pic_map_fdt()
203 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); in gpio_pic_map_fdt()
227 *irqp = irq; in gpio_pic_map_fdt()
237 u_int irq; in gpio_pic_map_gpio() local
239 irq = dag->gpio_pin_num; in gpio_pic_map_gpio()
240 if (irq >= sc->gpio_npins) { in gpio_pic_map_gpio()
241 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); in gpio_pic_map_gpio()
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| /freebsd/sys/contrib/device-tree/src/arm/intel/ixp/ |
| H A D | intel-ixp43x-gateworks-gw2358.dts | 129 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
130 * connected to IRQ 10 etc. I find this highly unlikely so I
138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
139 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
140 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
141 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
143 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
144 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
145 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
146 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_intr.c | 215 int irq, num; in bcm2835_intc_intr() local
219 irq = bcm2835_intc_active_intr(sc); in bcm2835_intc_intr()
220 if (irq == -1) in bcm2835_intc_intr()
222 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, in bcm2835_intc_intr()
224 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); in bcm2835_intc_intr()
225 device_printf(sc->sc_dev, "Stray irq %u disabled\n", in bcm2835_intc_intr()
226 irq); in bcm2835_intc_intr()
257 u_int irq; in bcm_intc_map_intr() local
267 irq = daf->cells[0]; in bcm_intc_map_intr()
272 irq = daf->cells[1]; in bcm_intc_map_intr()
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| /freebsd/sys/dev/qat/qat_common/ |
| H A D | adf_isr.c | 64 "Failed to enable MSI-X IRQ(s)\n"); in adf_enable_msix()
75 "Failed to remap MSI-X IRQ(s)\n"); in adf_enable_msix()
173 /* Request msix irq for all banks unless SR-IOV enabled */ in adf_request_irqs()
179 msixe[i].irq = in adf_request_irqs()
184 if (msixe[i].irq == NULL) { in adf_request_irqs()
187 "failed to allocate IRQ for bundle %d\n", in adf_request_irqs()
193 msixe[i].irq, in adf_request_irqs()
202 "failed to enable IRQ for bundle %d\n", in adf_request_irqs()
207 msixe[i].irq); in adf_request_irqs()
208 msixe[i].irq = NULL; in adf_request_irqs()
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| /freebsd/sys/x86/isa/ |
| H A D | elcr.c | 42 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
43 * associated IRQ is edge triggered. If the bit is one, the IRQ is
53 #define ELCR_MASK(irq) (1 << (irq)) argument
93 elcr_read_trigger(u_int irq) in elcr_read_trigger() argument
97 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); in elcr_read_trigger()
98 if (elcr_status & ELCR_MASK(irq)) in elcr_read_trigger()
105 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
109 elcr_write_trigger(u_int irq, enum intr_trigger trigger) in elcr_write_trigger() argument
114 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); in elcr_write_trigger()
116 new_status = elcr_status | ELCR_MASK(irq); in elcr_write_trigger()
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | v3-v360epc-pci.txt | 40 interrupts = <17>; /* Bus error IRQ */
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
[all …]
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| /freebsd/sys/arm/mv/ |
| H A D | mv_ap806_sei.c | 82 u_int irq; member
116 bit = GICP_SEMR_BIT(sisrc->irq); in mv_ap806_sei_isrc_mask()
118 tmp = RD4(sc, GICP_SEMR(sisrc->irq)); in mv_ap806_sei_isrc_mask()
123 WR4(sc, GICP_SEMR(sisrc->irq), tmp); in mv_ap806_sei_isrc_mask()
132 WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq)); in mv_ap806_sei_isrc_eoi()
161 u_int irq; in mv_ap806_sei_map() local
174 irq = daf->cells[0]; in mv_ap806_sei_map()
176 *irqp = irq; in mv_ap806_sei_map()
186 u_int irq; in mv_ap806_sei_map_intr() local
190 rv = mv_ap806_sei_map(dev, data, &irq); in mv_ap806_sei_map_intr()
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| /freebsd/sys/riscv/vmm/ |
| H A D | vmm_aplic.c | 115 struct aplic_irq *irq; in aplic_handle_sourcecfg() local
121 irq = &aplic->irqs[i]; in aplic_handle_sourcecfg()
123 irq->sourcecfg = *val; in aplic_handle_sourcecfg()
125 *val = irq->sourcecfg; in aplic_handle_sourcecfg()
134 struct aplic_irq *irq; in aplic_set_enabled() local
146 irq = &aplic->irqs[i]; in aplic_set_enabled()
150 irq->state |= APLIC_IRQ_STATE_ENABLED; in aplic_set_enabled()
152 irq->state &= ~APLIC_IRQ_STATE_ENABLED; in aplic_set_enabled()
161 struct aplic_irq *irq; in aplic_handle_target() local
164 irq = &aplic->irqs[i]; in aplic_handle_target()
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| /freebsd/sys/powerpc/powerpc/ |
| H A D | openpic.c | 76 u_int cpu, ipi, irq; in openpic_common_attach() local
180 for (irq = 0; irq < sc->sc_nirq; irq++) { in openpic_common_attach()
181 x = irq; /* irq == vector. */ in openpic_common_attach()
186 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); in openpic_common_attach()
203 for (irq = 0; irq < sc->sc_nirq; irq++) in openpic_common_attach()
204 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0); in openpic_common_attach()
207 for (irq = 0; irq < sc->sc_nirq; irq++) { in openpic_common_attach()
229 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused) in openpic_bind() argument
260 openpic_write(sc, OPENPIC_IDEST(irq), mask); in openpic_bind()
264 openpic_config(device_t dev, u_int irq, enum intr_trigger trig, in openpic_config() argument
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| /freebsd/sys/riscv/riscv/ |
| H A D | aplic.c | 63 u_int irq; member
77 #define APLIC_DOMAIN_CFG_DM (1UL << 2) /* IRQ delivery mode */
210 aplic_irq_dispatch(struct aplic_softc *sc, u_int irq, u_int prio, in aplic_irq_dispatch() argument
215 src = &sc->isrcs[irq]; in aplic_irq_dispatch()
219 device_printf(sc->dev, "Stray irq %u detected\n", irq); in aplic_irq_dispatch()
228 u_int prio, irq; in aplic_intr() local
237 irq = APLIC_IDC_CLAIMI_IRQ(claimi); in aplic_intr()
239 KASSERT((irq != 0), ("Invalid IRQ 0")); in aplic_intr()
242 aplic_irq_dispatch(sc, irq, prio, tf); in aplic_intr()
258 aplic_write(sc, APLIC_CLRIENUM, src->irq); in aplic_disable_intr()
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| H A D | intc.c | 66 u_int irq; member
169 isrcs[i].irq = i; in intc_attach()
190 u_int irq; in intc_disable_intr() local
192 irq = ((struct intc_irqsrc *)isrc)->irq; in intc_disable_intr()
193 if (irq >= INTC_NIRQS) in intc_disable_intr()
194 panic("%s: Unsupported IRQ %u", __func__, irq); in intc_disable_intr()
196 csr_clear(sie, 1ul << irq); in intc_disable_intr()
202 u_int irq; in intc_enable_intr() local
204 irq = ((struct intc_irqsrc *)isrc)->irq; in intc_enable_intr()
205 if (irq >= INTC_NIRQS) in intc_enable_intr()
[all …]
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