Lines Matching full:irq
118 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */
181 u_int irq; in gpio_pic_map_fdt() local
201 irq = daf->cells[0]; in gpio_pic_map_fdt()
202 if (irq >= sc->gpio_npins) { in gpio_pic_map_fdt()
203 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); in gpio_pic_map_fdt()
227 *irqp = irq; in gpio_pic_map_fdt()
237 u_int irq; in gpio_pic_map_gpio() local
239 irq = dag->gpio_pin_num; in gpio_pic_map_gpio()
240 if (irq >= sc->gpio_npins) { in gpio_pic_map_gpio()
241 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); in gpio_pic_map_gpio()
258 *irqp = irq; in gpio_pic_map_gpio()
286 u_int irq; in gpio_pic_map_intr() local
290 error = gpio_pic_map(sc, data, &irq, NULL); in gpio_pic_map_intr()
292 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; in gpio_pic_map_intr()
324 u_int icfg, irq, reg, shift, wrk; in gpio_pic_setup_intr() local
334 error = gpio_pic_map(sc, data, &irq, &mode); in gpio_pic_setup_intr()
337 if (gi->gi_irq != irq) in gpio_pic_setup_intr()
353 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); in gpio_pic_setup_intr()
355 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); in gpio_pic_setup_intr()
373 if (irq < 16) { in gpio_pic_setup_intr()
375 shift = 2 * irq; in gpio_pic_setup_intr()
378 shift = 2 * (irq - 16); in gpio_pic_setup_intr()
385 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); in gpio_pic_setup_intr()
386 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); in gpio_pic_setup_intr()
399 u_int irq; in gpio_pic_disable_intr() local
402 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; in gpio_pic_disable_intr()
405 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); in gpio_pic_disable_intr()
416 u_int irq; in gpio_pic_enable_intr() local
419 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; in gpio_pic_enable_intr()
422 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); in gpio_pic_enable_intr()
430 u_int irq; in gpio_pic_post_filter() local
433 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; in gpio_pic_post_filter()
437 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_filter()
444 u_int irq; in gpio_pic_post_ithread() local
447 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; in gpio_pic_post_ithread()
451 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_ithread()
480 device_printf(sc->dev, "Stray irq %u disabled\n", i); in gpio_pic_filter()
494 uint32_t irq; in gpio_pic_register_isrcs() local
498 for (irq = 0; irq < NGPIO; irq++) { in gpio_pic_register_isrcs()
499 sc->gpio_pic_irqsrc[irq].gi_irq = irq; in gpio_pic_register_isrcs()
500 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM; in gpio_pic_register_isrcs()
502 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, in gpio_pic_register_isrcs()
503 sc->dev, 0, "%s,%u", name, irq); in gpio_pic_register_isrcs()
800 int i, irq, unit; in imx51_gpio_attach() local
837 for (irq = 0; irq < 2; irq++) { in imx51_gpio_attach()
839 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, in imx51_gpio_attach()
840 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { in imx51_gpio_attach()
877 int irq; in imx51_gpio_detach() local
894 for (irq = 0; irq < NUM_IRQRES; irq++) { in imx51_gpio_detach()
895 if (sc->gpio_ih[irq]) in imx51_gpio_detach()
896 bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES], in imx51_gpio_detach()
897 sc->gpio_ih[irq]); in imx51_gpio_detach()