Lines Matching full:irq
42 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
43 * associated IRQ is edge triggered. If the bit is one, the IRQ is
53 #define ELCR_MASK(irq) (1 << (irq)) argument
93 elcr_read_trigger(u_int irq) in elcr_read_trigger() argument
97 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); in elcr_read_trigger()
98 if (elcr_status & ELCR_MASK(irq)) in elcr_read_trigger()
105 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
109 elcr_write_trigger(u_int irq, enum intr_trigger trigger) in elcr_write_trigger() argument
114 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); in elcr_write_trigger()
116 new_status = elcr_status | ELCR_MASK(irq); in elcr_write_trigger()
118 new_status = elcr_status & ~ELCR_MASK(irq); in elcr_write_trigger()
122 if (irq >= 8) in elcr_write_trigger()