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/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0+
127 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
132 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in sun8i_hdmi_phy_set_polarity()
135 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in sun8i_hdmi_phy_set_polarity()
138 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
142 static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, in sun8i_a83t_hdmi_phy_config() argument
146 unsigned int clk_rate = mode->crtc_clock * 1000; in sun8i_a83t_hdmi_phy_config()
147 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
149 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
151 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
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H A Dsun8i_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
37 if (mode->clock > 297000) in sun8i_dw_hdmi_mode_valid_a83t()
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
52 if (mode->clock > 594000) in sun8i_dw_hdmi_mode_valid_h6()
70 remote = of_graph_get_remote_node(node, 0, -1); in sun8i_dw_hdmi_find_possible_crtcs()
104 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
107 if (!pdev->dev.of_node) in sun8i_dw_hdmi_bind()
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/linux/Documentation/devicetree/bindings/phy/
H A Damlogic,meson8-hdmi-tx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 The HDMI TX PHY node should be the child of a syscon node with the
16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
23 pattern: "^hdmi-phy@[0-9a-f]+$"
27 - items:
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H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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H A Dqcom,hdmi-phy-other.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
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H A Dqcom,hdmi-phy-qmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon QMP HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8996
17 - qcom,hdmi-phy-8998
22 reg-names:
24 - const: hdmi_pll
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
58 struct hdmi_phy *phy; member
67 /* the encoder we are hooked to (outside of hdmi block) */ argument
70 bool hdmi_mode; /* are we in hdmi mode? */ argument
109 struct hdmi *hdmi; member
114 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
116 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
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H A Dhdmi_bridge.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "hdmi.h"
16 struct drm_device *dev = bridge->dev; in msm_hdmi_power_on()
18 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on() local
19 const struct hdmi_platform_config *config = hdmi->config; in msm_hdmi_power_on()
22 pm_runtime_get_sync(&hdmi->pdev->dev); in msm_hdmi_power_on()
24 ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs); in msm_hdmi_power_on()
26 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret); in msm_hdmi_power_on()
28 if (config->pwr_clk_cnt > 0) { in msm_hdmi_power_on()
29 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
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H A Dhdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "hdmi.h"
11 static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy) in msm_hdmi_phy_resource_init() argument
13 struct hdmi_phy_cfg *cfg = phy->cfg; in msm_hdmi_phy_resource_init()
14 struct device *dev = &phy->pdev->dev; in msm_hdmi_phy_resource_init()
17 phy->regs = devm_kcalloc(dev, cfg->num_regs, sizeof(phy->regs[0]), in msm_hdmi_phy_resource_init()
19 if (!phy->regs) in msm_hdmi_phy_resource_init()
20 return -ENOMEM; in msm_hdmi_phy_resource_init()
22 phy->clks = devm_kcalloc(dev, cfg->num_clks, sizeof(phy->clks[0]), in msm_hdmi_phy_resource_init()
24 if (!phy->clks) in msm_hdmi_phy_resource_init()
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H A Dhdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <sound/hdmi-codec.h>
17 #include "hdmi.h"
19 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) in msm_hdmi_set_mode() argument
24 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
27 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
29 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
38 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
39 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
40 DBG("HDMI Core: %s, HDMI_CTRL=0x%08x", in msm_hdmi_set_mode()
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-hdmi-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t HDMI PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a83t-hdmi-phy
20 - allwinner,sun8i-h3-hdmi-phy
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H A Dallwinner,sun8i-a83t-dw-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
19 - Chen-Yu Tsai <wens@csie.org>
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H A Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: /schemas/sound/dai-common.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC HDMI
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/hdmi.h>
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
39 #include "dw-hdmi-audio.h"
40 #include "dw-hdmi-cec.h"
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
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/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 * Configure and power up the PHY PLL in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
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H A Dsti_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/hdmi.h>
13 #include <media/cec-notifier.h>
25 bool (*start)(struct sti_hdmi *hdmi);
26 void (*stop)(struct sti_hdmi *hdmi);
39 * STI hdmi structure
44 * @regs: hdmi register
46 * @clk_pix: hdmi pixel clock
47 * @clk_tmds: hdmi tmds clock
48 * @clk_phy: hdmi phy clock
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/linux/drivers/gpu/drm/rockchip/
H A Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/phy/phy.h>
38 /* need to be unset if hdmi or i2c should control voltage */
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
62 * @lcdsel_big: reg value of selecting vop big for HDMI
63 * @lcdsel_lit: reg value of selecting vop little for HDMI
82 struct dw_hdmi *hdmi; member
83 struct phy *phy; member
199 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
201 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "phy-mtk-hdmi.h"
9 static int mtk_hdmi_phy_power_on(struct phy *phy);
10 static int mtk_hdmi_phy_power_off(struct phy *phy);
11 static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts);
25 static int mtk_hdmi_phy_power_on(struct phy *phy) in mtk_hdmi_phy_power_on() argument
27 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy); in mtk_hdmi_phy_power_on()
30 ret = clk_prepare_enable(hdmi_phy->pll); in mtk_hdmi_phy_power_on()
34 hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy); in mtk_hdmi_phy_power_on()
38 static int mtk_hdmi_phy_power_off(struct phy *phy) in mtk_hdmi_phy_power_off() argument
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI driver for OMAP5
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
14 #define DSS_SUBSYS_NAME "HDMI"
31 #include <sound/omap-hdmi-audio.h>
41 static int hdmi_runtime_get(struct omap_hdmi *hdmi) in hdmi_runtime_get() argument
47 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
49 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
55 static void hdmi_runtime_put(struct omap_hdmi *hdmi) in hdmi_runtime_put() argument
61 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI driver for OMAP5
14 #define DSS_SUBSYS_NAME "HDMI"
32 #include <sound/omap-hdmi-audio.h>
38 static struct omap_hdmi hdmi; variable
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
76 * time, turn off the PHY, clear interrupts, and restart, which in hdmi_irq_handler()
85 * setting the PHY to LDOON. To ignore those, we force the RXDET in hdmi_irq_handler()
[all …]
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
14 with a companion PHY IP.
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
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/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
36 * DOC: HDMI Output
38 * HDMI Output is composed of :
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
50 * | Synopsys HDMI | HDMI PHY |=> TMDS
[all …]
/linux/drivers/gpu/drm/msm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 ccflags-y := -I $(src)
3 ccflags-y += -I $(obj)/generated
4 ccflags-y += -I $(src)/disp/dpu1
5 ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(src)/dsi
6 ccflags-$(CONFIG_DRM_MSM_DP) += -I $(src)/dp
8 adreno-y := \
28 adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
30 adreno-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
32 msm-display-$(CONFIG_DRM_MSM_HDMI) += \
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