xref: /linux/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
9
10maintainers:
11  - Neil Armstrong <neil.armstrong@linaro.org>
12
13allOf:
14  - $ref: /schemas/sound/dai-common.yaml#
15
16description: |
17  The Amlogic Meson Synopsys Designware Integration is composed of
18  - A Synopsys DesignWare HDMI Controller IP
19  - A TOP control block controlling the Clocks and PHY
20  - A custom HDMI PHY in order to convert video to TMDS signal
21   ___________________________________
22  |            HDMI TOP               |<= HPD
23  |___________________________________|
24  |                  |                |
25  |  Synopsys HDMI   |   HDMI PHY     |=> TMDS
26  |    Controller    |________________|
27  |___________________________________|<=> DDC
28
29  The HDMI TOP block only supports HPD sensing.
30  The Synopsys HDMI Controller interrupt is routed through the
31  TOP Block interrupt.
32  Communication to the TOP Block and the Synopsys HDMI Controller is done
33  via a pair of dedicated addr+read/write registers.
34  The HDMI PHY is configured by registers in the HHI register block.
35
36  Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
37  selects either the ENCI encoder for the 576i or 480i formats or the ENCP
38  encoder for all the other formats including interlaced HD formats.
39
40  The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
41  DVI timings for the HDMI controller.
42
43  Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
44  HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
45  audio source interfaces.
46
47properties:
48  compatible:
49    oneOf:
50      - items:
51          - enum:
52              - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
53              - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
54              - amlogic,meson-gxm-dw-hdmi # GXM (S912)
55          - const: amlogic,meson-gx-dw-hdmi
56      - enum:
57          - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
58
59  reg:
60    maxItems: 1
61
62  interrupts:
63    maxItems: 1
64
65  clocks:
66    minItems: 3
67
68  clock-names:
69    items:
70      - const: isfr
71      - const: iahb
72      - const: venci
73
74  power-domains:
75    maxItems: 1
76    description: phandle to the associated power domain
77
78  resets:
79    minItems: 3
80
81  reset-names:
82    items:
83      - const: hdmitx_apb
84      - const: hdmitx
85      - const: hdmitx_phy
86
87  hdmi-supply:
88    description: phandle to an external 5V regulator to power the HDMI logic
89
90  port@0:
91    $ref: /schemas/graph.yaml#/properties/port
92    description:
93      A port node pointing to the VENC Input port node.
94
95  port@1:
96    $ref: /schemas/graph.yaml#/properties/port
97    description:
98      A port node pointing to the TMDS Output port node.
99
100  "#address-cells":
101    const: 1
102
103  "#size-cells":
104    const: 0
105
106  "#sound-dai-cells":
107    const: 0
108
109  sound-name-prefix: true
110
111required:
112  - compatible
113  - reg
114  - interrupts
115  - clocks
116  - clock-names
117  - resets
118  - reset-names
119  - port@0
120  - port@1
121  - "#address-cells"
122  - "#size-cells"
123
124additionalProperties: false
125
126examples:
127  - |
128    hdmi_tx: hdmi-tx@c883a000 {
129        compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
130        reg = <0xc883a000 0x1c>;
131        interrupts = <57>;
132        resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
133        reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
134        clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
135        clock-names = "isfr", "iahb", "venci";
136        power-domains = <&pd_vpu>;
137        #address-cells = <1>;
138        #size-cells = <0>;
139
140        /* VPU VENC Input */
141        hdmi_tx_venc_port: port@0 {
142            reg = <0>;
143
144            hdmi_tx_in: endpoint {
145                remote-endpoint = <&hdmi_tx_out>;
146            };
147        };
148
149        /* TMDS Output */
150        hdmi_tx_tmds_port: port@1 {
151             reg = <1>;
152
153             hdmi_tx_tmds_out: endpoint {
154                 remote-endpoint = <&hdmi_connector_in>;
155             };
156        };
157    };
158