Lines Matching +full:hdmi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "hdmi.h"
18 struct drm_device *dev = bridge->dev;
20 struct hdmi *hdmi = hdmi_bridge->hdmi;
21 const struct hdmi_platform_config *config = hdmi->config;
24 pm_runtime_get_sync(&hdmi->pdev->dev);
26 ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs);
28 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret);
30 if (config->pwr_clk_cnt > 0) {
31 DBG("pixclock: %lu", hdmi->pixclock);
32 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
34 DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n",
35 config->pwr_clk_names[0], ret);
39 for (i = 0; i < config->pwr_clk_cnt; i++) {
40 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
42 DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n",
43 config->pwr_clk_names[i], ret);
50 struct drm_device *dev = bridge->dev;
52 struct hdmi *hdmi = hdmi_bridge->hdmi;
53 const struct hdmi_platform_config *config = hdmi->config;
61 for (i = 0; i < config->pwr_clk_cnt; i++)
62 clk_disable_unprepare(hdmi->pwr_clks[i]);
64 ret = regulator_bulk_disable(config->pwr_reg_cnt, hdmi->pwr_regs);
66 DRM_DEV_ERROR(dev->dev, "failed to disable pwr regulator: %d\n", ret);
68 pm_runtime_put(&hdmi->pdev->dev);
75 static int msm_hdmi_config_avi_infoframe(struct hdmi *hdmi,
82 if (len != HDMI_INFOFRAME_SIZE(AVI) || len - 3 > sizeof(buf)) {
83 DRM_DEV_ERROR(&hdmi->pdev->dev,
85 return -EINVAL;
94 memcpy(buf, &buffer[3], len - 3);
99 hdmi_write(hdmi, REG_HDMI_AVI_INFO(i), buf[i]);
101 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
104 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val);
106 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
109 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
114 static int msm_hdmi_config_audio_infoframe(struct hdmi *hdmi,
120 DRM_DEV_ERROR(&hdmi->pdev->dev,
122 return -EINVAL;
125 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0,
131 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1,
137 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
142 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val);
147 static int msm_hdmi_config_spd_infoframe(struct hdmi *hdmi,
154 if (len != HDMI_INFOFRAME_SIZE(SPD) || len - 3 > sizeof(buf)) {
155 DRM_DEV_ERROR(&hdmi->pdev->dev,
157 return -EINVAL;
161 hdmi_write(hdmi, REG_HDMI_GENERIC1_HDR,
166 memcpy(buf, &buffer[3], len - 3);
169 hdmi_write(hdmi, REG_HDMI_GENERIC1(i), buf[i]);
171 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL);
175 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val);
180 static int msm_hdmi_config_hdmi_infoframe(struct hdmi *hdmi,
188 len - 3 > sizeof(buf)) {
189 DRM_DEV_ERROR(&hdmi->pdev->dev,
190 "failed to configure HDMI infoframe\n");
191 return -EINVAL;
195 hdmi_write(hdmi, REG_HDMI_GENERIC0_HDR,
200 memcpy(buf, &buffer[3], len - 3);
203 hdmi_write(hdmi, REG_HDMI_GENERIC0(i), buf[i]);
205 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL);
210 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val);
219 struct hdmi *hdmi = hdmi_bridge->hdmi;
224 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0);
227 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val);
229 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
231 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
236 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0);
241 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val);
243 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
245 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
250 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL);
254 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val);
259 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL);
264 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val);
269 drm_dbg_driver(hdmi_bridge->base.dev, "Unsupported infoframe type %x\n", type);
280 struct hdmi *hdmi = hdmi_bridge->hdmi;
286 return msm_hdmi_config_avi_infoframe(hdmi, buffer, len);
288 return msm_hdmi_config_audio_infoframe(hdmi, buffer, len);
290 return msm_hdmi_config_spd_infoframe(hdmi, buffer, len);
292 return msm_hdmi_config_hdmi_infoframe(hdmi, buffer, len);
294 drm_dbg_driver(hdmi_bridge->base.dev, "Unsupported infoframe type %x\n", type);
299 static void msm_hdmi_set_timings(struct hdmi *hdmi,
306 struct hdmi *hdmi = hdmi_bridge->hdmi;
307 struct hdmi_phy *phy = hdmi->phy;
308 struct drm_encoder *encoder = bridge->encoder;
317 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
319 hdmi->pixclock = conn_state->hdmi.tmds_char_rate;
321 msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode);
323 if (!hdmi->power_on) {
324 msm_hdmi_phy_resource_enable(phy);
326 hdmi->power_on = true;
327 if (connector->display_info.is_hdmi)
328 msm_hdmi_audio_update(hdmi);
333 msm_hdmi_phy_powerup(phy, hdmi->pixclock);
335 msm_hdmi_set_mode(hdmi, true);
337 if (hdmi->hdcp_ctrl)
338 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
345 struct hdmi *hdmi = hdmi_bridge->hdmi;
346 struct hdmi_phy *phy = hdmi->phy;
348 if (hdmi->hdcp_ctrl)
349 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
352 msm_hdmi_set_mode(hdmi, false);
354 msm_hdmi_phy_powerdown(phy);
356 if (hdmi->power_on) {
358 hdmi->power_on = false;
359 if (hdmi->connector->display_info.is_hdmi)
360 msm_hdmi_audio_update(hdmi);
361 msm_hdmi_phy_resource_disable(phy);
365 static void msm_hdmi_set_timings(struct hdmi *hdmi,
371 hstart = mode->htotal - mode->hsync_start;
372 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
374 vstart = mode->vtotal - mode->vsync_start - 1;
375 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
378 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
380 hdmi_write(hdmi, REG_HDMI_TOTAL,
381 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
382 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
384 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
387 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
391 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
392 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
393 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
394 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
398 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
400 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
406 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
408 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
410 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
413 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
415 if (hdmi->connector->display_info.is_hdmi)
416 msm_hdmi_audio_update(hdmi);
423 struct hdmi *hdmi = hdmi_bridge->hdmi;
427 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL);
428 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE);
430 drm_edid = drm_edid_read_ddc(connector, hdmi->i2c);
432 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
442 struct hdmi *hdmi = hdmi_bridge->hdmi;
443 const struct hdmi_platform_config *config = hdmi->config;
444 struct msm_drm_private *priv = bridge->dev->dev_private;
445 struct msm_kms *kms = priv->kms;
452 if (kms->funcs->round_pixclk)
453 actual = kms->funcs->round_pixclk(kms,
455 hdmi_bridge->hdmi->encoder);
456 else if (config->pwr_clk_cnt > 0)
457 actual = clk_round_rate(hdmi->pwr_clks[0], tmds_rate);
489 struct drm_bridge *bridge = &hdmi_bridge->base;
495 int msm_hdmi_bridge_init(struct hdmi *hdmi)
501 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
504 return -ENOMEM;
506 hdmi_bridge->hdmi = hdmi;
507 INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work);
509 bridge = &hdmi_bridge->base;
510 bridge->funcs = &msm_hdmi_bridge_funcs;
511 bridge->ddc = hdmi->i2c;
512 bridge->type = DRM_MODE_CONNECTOR_HDMIA;
513 bridge->vendor = "Qualcomm";
514 bridge->product = "Snapdragon";
515 bridge->ops = DRM_BRIDGE_OP_HPD |
519 bridge->hdmi_audio_max_i2s_playback_channels = 8;
520 bridge->hdmi_audio_dev = &hdmi->pdev->dev;
521 bridge->hdmi_audio_dai_port = -1;
523 ret = devm_drm_bridge_add(hdmi->dev->dev, bridge);
527 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
531 hdmi->bridge = bridge;