Lines Matching +full:hdmi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/hdmi.h>
20 #include <linux/dma-mapping.h>
23 #include <media/cec-notifier.h>
25 #include <uapi/linux/media-bus-format.h>
39 #include "dw-hdmi-audio.h"
40 #include "dw-hdmi-cec.h"
41 #include "dw-hdmi.h"
48 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
126 int (*configure)(struct dw_hdmi *hdmi,
155 } phy;
169 enum drm_connector_force force; /* mutex-protected force state */
174 u8 phy_mask; /* desired phy int mask settings */
189 void (*enable_audio)(struct dw_hdmi *hdmi);
190 void (*disable_audio)(struct dw_hdmi *hdmi);
208 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
210 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
213 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
217 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
222 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
224 if (hdmi->plugged_cb && hdmi->codec_dev)
225 hdmi->plugged_cb(hdmi->codec_dev, plugged);
228 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
233 mutex_lock(&hdmi->mutex);
234 hdmi->plugged_cb = fn;
235 hdmi->codec_dev = codec_dev;
236 plugged = hdmi->last_connector_result == connector_status_connected;
237 handle_plugged_change(hdmi, plugged);
238 mutex_unlock(&hdmi->mutex);
244 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
246 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
249 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
252 hdmi_modb(hdmi, data << shift, mask, reg);
255 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
257 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
260 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
265 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
268 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
271 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
272 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
276 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
280 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
284 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
287 if (!hdmi->unwedge_state)
290 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
310 * its HDMI ports. It happened when the TV was powered on while the
324 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
326 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
331 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
333 struct dw_hdmi_i2c *i2c = hdmi->i2c;
336 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
339 if (!dw_hdmi_i2c_unwedge(hdmi))
340 return -EAGAIN;
343 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
345 return -EAGAIN;
349 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
350 return -EIO;
355 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
358 struct dw_hdmi_i2c *i2c = hdmi->i2c;
361 if (!i2c->is_regaddr) {
362 dev_dbg(hdmi->dev, "set read register address to 0\n");
363 i2c->slave_reg = 0x00;
364 i2c->is_regaddr = true;
367 while (length--) {
368 reinit_completion(&i2c->cmp);
370 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
371 if (i2c->is_segment)
372 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
375 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
378 ret = dw_hdmi_i2c_wait(hdmi);
382 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
384 i2c->is_segment = false;
389 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
392 struct dw_hdmi_i2c *i2c = hdmi->i2c;
395 if (!i2c->is_regaddr) {
397 i2c->slave_reg = buf[0];
398 length--;
400 i2c->is_regaddr = true;
403 while (length--) {
404 reinit_completion(&i2c->cmp);
406 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
407 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
408 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
411 ret = dw_hdmi_i2c_wait(hdmi);
422 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
423 struct dw_hdmi_i2c *i2c = hdmi->i2c;
429 * The internal I2C controller does not support the multi-byte
434 return -EOPNOTSUPP;
436 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
440 dev_dbg(hdmi->dev,
443 return -EOPNOTSUPP;
447 mutex_lock(&i2c->lock);
450 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
453 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
456 i2c->is_regaddr = false;
459 i2c->is_segment = false;
462 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
465 i2c->is_segment = true;
466 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
467 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
470 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
473 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
484 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
487 mutex_unlock(&i2c->lock);
502 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
508 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
510 return ERR_PTR(-ENOMEM);
512 mutex_init(&i2c->lock);
513 init_completion(&i2c->cmp);
515 adap = &i2c->adap;
516 adap->owner = THIS_MODULE;
517 adap->dev.parent = hdmi->dev;
518 adap->algo = &dw_hdmi_algorithm;
519 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
520 i2c_set_adapdata(adap, hdmi);
524 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
525 devm_kfree(hdmi->dev, i2c);
529 hdmi->i2c = i2c;
531 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
536 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
540 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
543 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
547 hdmi_writeb(hdmi, ((cts >> 16) &
552 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
553 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
554 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
556 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
557 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
558 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
631 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
638 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
639 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
643 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
653 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
659 * can be up to 20 bits in total, so we need 64-bit math. Also
668 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
676 spin_lock_irq(&hdmi->audio_lock);
677 hdmi->audio_n = n;
678 hdmi->audio_cts = cts;
679 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
680 spin_unlock_irq(&hdmi->audio_lock);
683 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
685 mutex_lock(&hdmi->audio_mutex);
686 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
687 mutex_unlock(&hdmi->audio_mutex);
690 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
692 mutex_lock(&hdmi->audio_mutex);
693 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
694 hdmi->sample_rate);
695 mutex_unlock(&hdmi->audio_mutex);
698 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
700 mutex_lock(&hdmi->audio_mutex);
701 hdmi->sample_width = width;
702 mutex_unlock(&hdmi->audio_mutex);
706 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
708 mutex_lock(&hdmi->audio_mutex);
709 hdmi->sample_non_pcm = non_pcm;
710 mutex_unlock(&hdmi->audio_mutex);
714 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
716 mutex_lock(&hdmi->audio_mutex);
717 hdmi->sample_rate = rate;
718 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
719 hdmi->sample_rate);
720 mutex_unlock(&hdmi->audio_mutex);
724 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
728 mutex_lock(&hdmi->audio_mutex);
729 hdmi->channels = cnt;
740 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
744 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
747 mutex_unlock(&hdmi->audio_mutex);
751 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
753 mutex_lock(&hdmi->audio_mutex);
755 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
757 mutex_unlock(&hdmi->audio_mutex);
761 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
764 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
766 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
767 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
770 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
772 if (!hdmi->curr_conn)
775 return hdmi->curr_conn->eld;
778 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
780 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
782 int ch_mask = BIT(hdmi->channels) - 1;
784 switch (hdmi->sample_rate) {
817 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
818 hdmi_enable_audio_clk(hdmi, true);
820 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
821 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
822 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
823 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
824 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
825 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
826 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
827 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
829 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
830 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
831 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
833 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3);
836 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
837 hdmi->sample_width == 32 && hdmi->sample_non_pcm)
838 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
840 if (pdata->enable_audio)
841 pdata->enable_audio(hdmi,
842 hdmi->channels,
843 hdmi->sample_width,
844 hdmi->sample_rate,
845 hdmi->sample_non_pcm);
848 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
850 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
852 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
854 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3);
855 if (pdata->disable_audio)
856 pdata->disable_audio(hdmi);
858 hdmi_enable_audio_clk(hdmi, false);
861 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
863 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
866 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
868 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
871 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
873 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
874 hdmi_enable_audio_clk(hdmi, true);
877 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
879 hdmi_enable_audio_clk(hdmi, false);
882 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
886 spin_lock_irqsave(&hdmi->audio_lock, flags);
887 hdmi->audio_enable = true;
888 if (hdmi->enable_audio)
889 hdmi->enable_audio(hdmi);
890 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
894 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
898 spin_lock_irqsave(&hdmi->audio_lock, flags);
899 hdmi->audio_enable = false;
900 if (hdmi->disable_audio)
901 hdmi->disable_audio(hdmi);
902 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
999 static void hdmi_video_sample(struct dw_hdmi *hdmi)
1004 switch (hdmi->hdmi_data.enc_in_bus_format) {
1052 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1058 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1059 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1060 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1061 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1062 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1063 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1064 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1067 static int is_color_space_conversion(struct dw_hdmi *hdmi)
1069 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1072 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1073 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1076 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1079 static int is_color_space_decimation(struct dw_hdmi *hdmi)
1081 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1084 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
1085 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
1091 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1093 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1096 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1097 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1103 static bool is_csc_needed(struct dw_hdmi *hdmi)
1105 return is_color_space_conversion(hdmi) ||
1106 is_color_space_decimation(hdmi) ||
1107 is_color_space_interpolation(hdmi);
1110 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1117 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1118 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1121 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1126 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1132 hdmi->hdmi_data.rgb_limited_range) {
1142 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1143 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1144 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1145 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1146 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1147 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1150 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1154 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1161 if (is_color_space_interpolation(hdmi))
1163 else if (is_color_space_decimation(hdmi))
1166 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1185 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1186 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1189 dw_hdmi_update_csc_coeffs(hdmi);
1193 * HDMI video packetizer is used to packetize the data.
1197 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1202 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1207 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1208 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1209 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1211 hdmi->hdmi_data.enc_out_bus_format)) {
1229 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1231 hdmi->hdmi_data.enc_out_bus_format)) {
1255 ((hdmi_data->pix_repet_factor <<
1258 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1261 * Source shall only send GCPs with non-zero CD to sinks
1264 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
1266 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
1271 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
1273 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1277 if (hdmi_data->pix_repet_factor > 1) {
1285 hdmi_modb(hdmi, vp_conf,
1289 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1292 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1310 hdmi_modb(hdmi, vp_conf,
1314 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1319 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1323 /* -----------------------------------------------------------------------------
1324 * Synopsys PHY Handling
1327 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1330 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1334 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1338 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1339 if (msec-- == 0)
1343 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1348 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1351 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1352 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1353 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1355 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1357 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1359 hdmi_phy_wait_i2c_done(hdmi, 1000);
1364 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1368 if (hdmi->version < 0x200a)
1372 if (!hdmi->ddc)
1375 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1376 if (!display->hdmi.scdc.supported ||
1377 !display->hdmi.scdc.scrambling.supported)
1384 if (!display->hdmi.scdc.scrambling.low_rates &&
1385 display->max_tmds_clock <= 340000)
1393 * - The Source shall suspend transmission of the TMDS clock and data
1394 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1396 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1402 * the PHY configuration callback.
1404 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1407 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1409 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1410 if (dw_hdmi_support_scdc(hdmi, display)) {
1412 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);
1414 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);
1419 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1421 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1426 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1428 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1433 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1435 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1440 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1442 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1448 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1450 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1456 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1458 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1463 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1465 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1470 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
1472 /* PHY reset. The reset signal is active low on Gen1 PHYs. */
1473 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1474 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1478 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
1480 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1481 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1482 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1486 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1488 hdmi_phy_test_clear(hdmi, 1);
1489 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1490 hdmi_phy_test_clear(hdmi, 0);
1494 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1496 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1500 if (phy->gen == 1) {
1501 dw_hdmi_phy_enable_tmds(hdmi, 0);
1502 dw_hdmi_phy_enable_powerdown(hdmi, true);
1506 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1509 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1513 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1521 dev_warn(hdmi->dev, "PHY failed to power down\n");
1523 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1525 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1528 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1530 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1534 if (phy->gen == 1) {
1535 dw_hdmi_phy_enable_powerdown(hdmi, false);
1538 dw_hdmi_phy_enable_tmds(hdmi, 0);
1539 dw_hdmi_phy_enable_tmds(hdmi, 1);
1543 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1544 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1546 /* Wait for PHY PLL lock */
1548 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1556 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1557 return -ETIMEDOUT;
1560 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1565 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1566 * information the DWC MHL PHY has the same register layout and is thus also
1569 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1573 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1574 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1575 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1577 /* TOFIX Will need 420 specific PHY configuration tables */
1579 /* PLL/MPLL Cfg - always match on final entry */
1580 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1581 if (mpixelclock <= mpll_config->mpixelclock)
1584 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1585 if (mpixelclock <= curr_ctrl->mpixelclock)
1588 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1589 if (mpixelclock <= phy_config->mpixelclock)
1592 if (mpll_config->mpixelclock == ~0UL ||
1593 curr_ctrl->mpixelclock == ~0UL ||
1594 phy_config->mpixelclock == ~0UL)
1595 return -EINVAL;
1597 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1599 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1601 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1604 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1605 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1608 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1609 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1611 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1615 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1621 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1624 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1625 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1626 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1627 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1630 dw_hdmi_phy_power_off(hdmi);
1632 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1635 if (phy->has_svsret)
1636 dw_hdmi_phy_enable_svsret(hdmi, 1);
1638 dw_hdmi_phy_gen2_reset(hdmi);
1640 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1642 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1644 /* Write to the PHY as configured by the platform */
1645 if (pdata->configure_phy)
1646 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1648 ret = phy->configure(hdmi, pdata, mpixelclock);
1650 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1659 return dw_hdmi_phy_power_on(hdmi);
1662 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1668 /* HDMI Phy spec says to do the phy initialization sequence twice */
1670 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1671 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1673 ret = hdmi_phy_configure(hdmi, display);
1681 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1683 dw_hdmi_phy_power_off(hdmi);
1686 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1689 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1694 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1697 u8 old_mask = hdmi->phy_mask;
1700 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1702 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1704 if (old_mask != hdmi->phy_mask)
1705 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1709 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1712 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1715 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1716 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1720 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1723 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1725 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1738 /* -----------------------------------------------------------------------------
1739 * HDMI TX Setup
1742 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1746 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1752 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1755 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1757 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1761 static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1771 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1773 hdmi->hdmi_data.rgb_limited_range ?
1782 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1784 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1786 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1792 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1793 switch (hdmi->hdmi_data.enc_out_encoding) {
1795 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1803 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1840 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1846 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1854 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1858 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1860 /* AVI Data Byte 5- set up input and output pixel repetition */
1861 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1864 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1867 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1875 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1877 /* AVI Data Bytes 6-13 */
1878 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1879 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1880 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1881 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1882 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1883 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1884 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1885 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1888 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1909 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1913 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1916 /* Set the length of HDMI vendor specific InfoFrame payload */
1917 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1920 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1921 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1922 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1925 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1926 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1929 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1932 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1935 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1938 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1942 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1945 const struct drm_connector_state *conn_state = connector->state;
1951 if (!hdmi->plat_data->use_drm_infoframe)
1954 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1963 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1967 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1968 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1971 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1973 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1974 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1978 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1983 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1984 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1988 vmode->mpixelclock = mode->clock * 1000;
1990 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1992 vmode->mtmdsclock = vmode->mpixelclock;
1994 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1996 hdmi->hdmi_data.enc_out_bus_format)) {
1998 vmode->mtmdsclock = vmode->mpixelclock * 2;
2001 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
2004 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
2009 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2010 vmode->mtmdsclock /= 2;
2012 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2015 inv_val = (hdmi->hdmi_data.hdcp_enable ||
2016 (dw_hdmi_support_scdc(hdmi, display) &&
2017 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2018 hdmi_info->scdc.scrambling.low_rates)) ?
2022 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
2026 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
2030 inv_val |= (vmode->mdataenablepolarity ?
2034 if (hdmi->vic == 39)
2037 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2041 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2045 inv_val |= hdmi->sink_is_hdmi ?
2049 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
2051 hdisplay = mode->hdisplay;
2052 hblank = mode->htotal - mode->hdisplay;
2053 h_de_hs = mode->hsync_start - mode->hdisplay;
2054 hsync_len = mode->hsync_end - mode->hsync_start;
2060 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2067 vdisplay = mode->vdisplay;
2068 vblank = mode->vtotal - mode->vdisplay;
2069 v_de_vs = mode->vsync_start - mode->vdisplay;
2070 vsync_len = mode->vsync_end - mode->vsync_start;
2076 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2084 if (dw_hdmi_support_scdc(hdmi, display)) {
2085 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2086 hdmi_info->scdc.scrambling.low_rates) {
2096 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
2098 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
2102 drm_scdc_set_scrambling(hdmi->curr_conn, 1);
2106 * that the quasi-static configuration bit
2111 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2113 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
2115 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
2116 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2118 drm_scdc_set_scrambling(hdmi->curr_conn, 0);
2123 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
2124 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2127 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2128 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2131 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2132 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2135 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2138 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2139 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2142 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2145 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2146 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2149 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2152 /* HDMI Initialization Step B.4 */
2153 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2156 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2157 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2158 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2161 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2162 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2163 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2166 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2171 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2172 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2174 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2175 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2178 if (is_csc_needed(hdmi)) {
2179 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2180 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2182 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2185 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2186 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2188 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2194 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2206 * The number of iterations matters and depends on the HDMI TX revision
2215 switch (hdmi->version) {
2225 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2227 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2229 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2232 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2234 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2238 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2244 hdmi_disable_overflow_interrupts(hdmi);
2246 hdmi->vic = drm_match_cea_mode(mode);
2248 if (!hdmi->vic) {
2249 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2251 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2254 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2255 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2256 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2257 (hdmi->vic == 17) || (hdmi->vic == 18))
2258 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2260 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2262 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2263 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2265 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2266 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2269 if (hdmi->plat_data->input_bus_encoding)
2270 hdmi->hdmi_data.enc_in_encoding =
2271 hdmi->plat_data->input_bus_encoding;
2273 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2275 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2276 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2278 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2282 hdmi->hdmi_data.pix_repet_factor = 0;
2283 hdmi->hdmi_data.hdcp_enable = 0;
2284 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2286 /* HDMI Initialization Step B.1 */
2287 hdmi_av_composer(hdmi, &connector->display_info, mode);
2289 /* HDMI Initializateion Step B.2 */
2290 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2291 &connector->display_info,
2292 &hdmi->previous_mode);
2295 hdmi->phy.enabled = true;
2297 /* HDMI Initialization Step B.3 */
2298 dw_hdmi_enable_video_path(hdmi);
2300 if (hdmi->sink_has_audio) {
2301 dev_dbg(hdmi->dev, "sink has audio support\n");
2303 /* HDMI Initialization Step E - Configure audio */
2304 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2305 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2309 if (hdmi->sink_is_hdmi) {
2310 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2312 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2313 hdmi_config_AVI(hdmi, connector, mode);
2314 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2315 hdmi_config_drm_infoframe(hdmi, connector);
2317 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2320 hdmi_video_packetize(hdmi);
2321 hdmi_video_csc(hdmi);
2322 hdmi_video_sample(hdmi);
2323 hdmi_tx_hdcp_config(hdmi);
2325 dw_hdmi_clear_overflow(hdmi);
2330 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2339 * Disable top level interrupt bits in HDMI block
2341 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2345 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2348 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2349 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2350 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2351 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2352 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2353 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2354 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2355 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2356 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2357 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2358 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2359 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2360 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2361 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2364 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2365 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2366 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2367 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2368 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2369 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2370 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2371 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2372 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2373 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2375 /* Enable top level interrupt bits in HDMI block */
2378 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2381 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2383 hdmi->bridge_is_on = true;
2387 * is only be called when !hdmi->disabled.
2389 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2392 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2394 if (hdmi->phy.enabled) {
2395 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2396 hdmi->phy.enabled = false;
2399 hdmi->bridge_is_on = false;
2402 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2404 int force = hdmi->force;
2406 if (hdmi->disabled) {
2409 if (hdmi->rxsense)
2416 if (hdmi->bridge_is_on)
2417 dw_hdmi_poweroff(hdmi);
2419 if (!hdmi->bridge_is_on)
2420 dw_hdmi_poweron(hdmi);
2436 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2438 if (hdmi->phy.ops->update_hpd)
2439 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2440 hdmi->force, hdmi->disabled,
2441 hdmi->rxsense);
2444 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2448 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2449 hdmi->last_connector_result = result;
2454 static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi,
2460 if (!hdmi->ddc)
2463 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
2465 dev_dbg(hdmi->dev, "failed to get edid\n");
2470 * FIXME: This should use connector->display_info.is_hdmi and
2471 * connector->display_info.has_audio from a path that has read the EDID
2476 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2477 edid->width_cm, edid->height_cm);
2479 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2480 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2485 /* -----------------------------------------------------------------------------
2492 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2494 return dw_hdmi_detect(hdmi);
2499 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2504 drm_edid = dw_hdmi_edid_read(hdmi, connector);
2507 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2508 connector->display_info.source_physical_address);
2522 struct drm_crtc *crtc = new_state->crtc;
2533 crtc_state->mode_changed = true;
2541 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2544 mutex_lock(&hdmi->mutex);
2545 hdmi->force = connector->force;
2546 dw_hdmi_update_power(hdmi);
2547 dw_hdmi_update_phy_mask(hdmi);
2548 mutex_unlock(&hdmi->mutex);
2566 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2568 struct drm_connector *connector = &hdmi->connector;
2572 if (hdmi->version >= 0x200a)
2573 connector->ycbcr_420_allowed =
2574 hdmi->plat_data->ycbcr_420_allowed;
2576 connector->ycbcr_420_allowed = false;
2578 connector->interlace_allowed = 1;
2579 connector->polled = DRM_CONNECTOR_POLL_HPD;
2583 drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2586 hdmi->ddc);
2596 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2599 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2603 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2605 return -ENOMEM;
2607 mutex_lock(&hdmi->cec_notifier_mutex);
2608 hdmi->cec_notifier = notifier;
2609 mutex_unlock(&hdmi->cec_notifier_mutex);
2614 /* -----------------------------------------------------------------------------
2620 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2621 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2622 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2623 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2624 * - MEDIA_BUS_FMT_RGB888_1X24,
2625 * - MEDIA_BUS_FMT_YUV16_1X48,
2626 * - MEDIA_BUS_FMT_RGB161616_1X48,
2627 * - MEDIA_BUS_FMT_UYVY12_1X24,
2628 * - MEDIA_BUS_FMT_YUV12_1X36,
2629 * - MEDIA_BUS_FMT_RGB121212_1X36,
2630 * - MEDIA_BUS_FMT_UYVY10_1X20,
2631 * - MEDIA_BUS_FMT_YUV10_1X30,
2632 * - MEDIA_BUS_FMT_RGB101010_1X30,
2633 * - MEDIA_BUS_FMT_UYVY8_1X16,
2634 * - MEDIA_BUS_FMT_YUV8_1X24,
2646 struct drm_connector *conn = conn_state->connector;
2647 struct drm_display_info *info = &conn->display_info;
2648 struct drm_display_mode *mode = &crtc_state->mode;
2649 u8 max_bpc = conn_state->max_requested_bpc;
2650 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2651 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
2662 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2663 if (list_is_singular(&bridge->encoder->bridge_chain) ||
2664 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2675 if (conn->ycbcr_420_allowed &&
2680 if (max_bpc >= 16 && info->bpc == 16 &&
2681 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2684 if (max_bpc >= 12 && info->bpc >= 12 &&
2685 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2688 if (max_bpc >= 10 && info->bpc >= 10 &&
2689 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2709 if (max_bpc >= 16 && info->bpc == 16) {
2710 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2716 if (max_bpc >= 12 && info->bpc >= 12) {
2717 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2720 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2726 if (max_bpc >= 10 && info->bpc >= 10) {
2727 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2730 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2736 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2739 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2749 * - MEDIA_BUS_FMT_RGB888_1X24
2750 * - MEDIA_BUS_FMT_YUV8_1X24
2751 * - MEDIA_BUS_FMT_UYVY8_1X16
2752 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2753 * - MEDIA_BUS_FMT_RGB101010_1X30
2754 * - MEDIA_BUS_FMT_YUV10_1X30
2755 * - MEDIA_BUS_FMT_UYVY10_1X20
2756 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2757 * - MEDIA_BUS_FMT_RGB121212_1X36
2758 * - MEDIA_BUS_FMT_YUV12_1X36
2759 * - MEDIA_BUS_FMT_UYVY12_1X24
2760 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2761 * - MEDIA_BUS_FMT_RGB161616_1X48
2762 * - MEDIA_BUS_FMT_YUV16_1X48
2763 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2876 struct dw_hdmi *hdmi = bridge->driver_private;
2878 hdmi->hdmi_data.enc_out_bus_format =
2879 bridge_state->output_bus_cfg.format;
2881 hdmi->hdmi_data.enc_in_bus_format =
2882 bridge_state->input_bus_cfg.format;
2884 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2885 bridge_state->input_bus_cfg.format,
2886 bridge_state->output_bus_cfg.format);
2894 struct dw_hdmi *hdmi = bridge->driver_private;
2897 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
2900 return dw_hdmi_connector_create(hdmi);
2905 struct dw_hdmi *hdmi = bridge->driver_private;
2907 mutex_lock(&hdmi->cec_notifier_mutex);
2908 cec_notifier_conn_unregister(hdmi->cec_notifier);
2909 hdmi->cec_notifier = NULL;
2910 mutex_unlock(&hdmi->cec_notifier_mutex);
2918 struct dw_hdmi *hdmi = bridge->driver_private;
2919 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2922 /* We don't support double-clocked modes */
2923 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2926 if (pdata->mode_valid)
2927 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2937 struct dw_hdmi *hdmi = bridge->driver_private;
2939 mutex_lock(&hdmi->mutex);
2942 drm_mode_copy(&hdmi->previous_mode, mode);
2944 mutex_unlock(&hdmi->mutex);
2950 struct dw_hdmi *hdmi = bridge->driver_private;
2952 mutex_lock(&hdmi->mutex);
2953 hdmi->disabled = true;
2954 hdmi->curr_conn = NULL;
2955 dw_hdmi_update_power(hdmi);
2956 dw_hdmi_update_phy_mask(hdmi);
2957 handle_plugged_change(hdmi, false);
2958 mutex_unlock(&hdmi->mutex);
2964 struct dw_hdmi *hdmi = bridge->driver_private;
2968 bridge->encoder);
2970 mutex_lock(&hdmi->mutex);
2971 hdmi->disabled = false;
2972 hdmi->curr_conn = connector;
2973 dw_hdmi_update_power(hdmi);
2974 dw_hdmi_update_phy_mask(hdmi);
2975 handle_plugged_change(hdmi, true);
2976 mutex_unlock(&hdmi->mutex);
2981 struct dw_hdmi *hdmi = bridge->driver_private;
2983 return dw_hdmi_detect(hdmi);
2989 struct dw_hdmi *hdmi = bridge->driver_private;
2991 return dw_hdmi_edid_read(hdmi, connector);
3011 /* -----------------------------------------------------------------------------
3015 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3017 struct dw_hdmi_i2c *i2c = hdmi->i2c;
3020 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
3024 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
3026 i2c->stat = stat;
3028 complete(&i2c->cmp);
3035 struct dw_hdmi *hdmi = dev_id;
3039 if (hdmi->i2c)
3040 ret = dw_hdmi_i2c_irq(hdmi);
3042 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3044 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3051 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
3053 mutex_lock(&hdmi->mutex);
3055 if (!hdmi->force) {
3061 hdmi->rxsense = false;
3067 * at least iMX6S versions of the phy.
3070 hdmi->rxsense = true;
3072 dw_hdmi_update_power(hdmi);
3073 dw_hdmi_update_phy_mask(hdmi);
3075 mutex_unlock(&hdmi->mutex);
3081 struct dw_hdmi *hdmi = dev_id;
3085 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3086 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
3087 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
3102 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
3106 * load - in other words, there's something listening on the
3108 * power on the phy as HPD may be toggled by the sink to merely
3109 * ask the source to re-read the EDID.
3113 dw_hdmi_setup_rx_sense(hdmi,
3118 mutex_lock(&hdmi->cec_notifier_mutex);
3119 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3120 mutex_unlock(&hdmi->cec_notifier_mutex);
3131 dev_dbg(hdmi->dev, "EVENT=%s\n",
3135 if (hdmi->bridge.dev) {
3136 drm_helper_hpd_irq_event(hdmi->bridge.dev);
3137 drm_bridge_hpd_notify(&hdmi->bridge, status);
3141 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3142 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3151 .name = "DWC HDMI TX PHY",
3155 .name = "DWC MHL PHY + HEAC PHY",
3161 .name = "DWC MHL PHY",
3167 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3172 .name = "DWC HDMI 3D TX PHY",
3177 .name = "DWC HDMI 2.0 TX PHY",
3183 .name = "Vendor PHY",
3187 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3192 phy_type = hdmi->plat_data->phy_force_vendor ?
3194 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3198 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3199 dev_err(hdmi->dev,
3200 "Vendor HDMI PHY not supported by glue layer\n");
3201 return -ENODEV;
3204 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3205 hdmi->phy.data = hdmi->plat_data->phy_data;
3206 hdmi->phy.name = hdmi->plat_data->phy_name;
3213 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3214 hdmi->phy.name = dw_hdmi_phys[i].name;
3215 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3218 !hdmi->plat_data->configure_phy) {
3219 dev_err(hdmi->dev, "%s requires platform support\n",
3220 hdmi->phy.name);
3221 return -ENODEV;
3228 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3229 return -ENODEV;
3232 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3234 mutex_lock(&hdmi->mutex);
3235 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3236 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3237 mutex_unlock(&hdmi->mutex);
3240 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3242 mutex_lock(&hdmi->mutex);
3243 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3244 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3245 mutex_unlock(&hdmi->mutex);
3269 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3271 initialize_hdmi_ih_mutes(hdmi);
3274 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3278 dw_hdmi_i2c_init(hdmi);
3280 if (hdmi->phy.ops->setup_hpd)
3281 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3284 /* -----------------------------------------------------------------------------
3288 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi)
3292 if (!hdmi->plat_data->output_port)
3296 remote = of_graph_get_remote_node(hdmi->dev->of_node,
3297 hdmi->plat_data->output_port,
3298 -1);
3300 return -ENODEV;
3302 hdmi->next_bridge = of_drm_find_bridge(remote);
3304 if (!hdmi->next_bridge)
3305 return -EPROBE_DEFER;
3310 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
3312 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format);
3319 struct device *dev = &pdev->dev;
3320 struct device_node *np = dev->of_node;
3324 struct dw_hdmi *hdmi;
3335 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3336 if (!hdmi)
3337 return ERR_PTR(-ENOMEM);
3339 hdmi->plat_data = plat_data;
3340 hdmi->dev = dev;
3341 hdmi->sample_rate = 48000;
3342 hdmi->channels = 2;
3343 hdmi->disabled = true;
3344 hdmi->rxsense = true;
3345 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3346 hdmi->mc_clkdis = 0x7f;
3347 hdmi->last_connector_result = connector_status_disconnected;
3349 mutex_init(&hdmi->mutex);
3350 mutex_init(&hdmi->audio_mutex);
3351 mutex_init(&hdmi->cec_notifier_mutex);
3352 spin_lock_init(&hdmi->audio_lock);
3354 ret = dw_hdmi_parse_dt(hdmi);
3358 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3360 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3362 if (!hdmi->ddc) {
3363 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3364 return ERR_PTR(-EPROBE_DEFER);
3368 dev_dbg(hdmi->dev, "no ddc property found\n");
3371 if (!plat_data->regm) {
3374 of_property_read_u32(np, "reg-io-width", &val);
3378 hdmi->reg_shift = 2;
3384 dev_err(dev, "reg-io-width must be 1 or 4\n");
3385 return ERR_PTR(-EINVAL);
3389 hdmi->regs = devm_ioremap_resource(dev, iores);
3390 if (IS_ERR(hdmi->regs)) {
3391 ret = PTR_ERR(hdmi->regs);
3395 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3396 if (IS_ERR(hdmi->regm)) {
3398 ret = PTR_ERR(hdmi->regm);
3402 hdmi->regm = plat_data->regm;
3405 clk = devm_clk_get_enabled(hdmi->dev, "isfr");
3408 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3412 clk = devm_clk_get_enabled(hdmi->dev, "iahb");
3415 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3419 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec");
3422 if (ret != -EPROBE_DEFER)
3423 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3429 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3430 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3431 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3432 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3436 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3437 hdmi->version, prod_id0, prod_id1);
3438 ret = -ENODEV;
3442 ret = dw_hdmi_detect_phy(hdmi);
3446 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3447 hdmi->version >> 12, hdmi->version & 0xfff,
3449 hdmi->phy.name);
3451 dw_hdmi_init_hw(hdmi);
3461 dev_name(dev), hdmi);
3467 * N and cts values before enabling phy
3469 hdmi_init_clk_regenerator(hdmi);
3471 /* If DDC bus is not specified, try to register HDMI I2C bus */
3472 if (!hdmi->ddc) {
3474 hdmi->pinctrl = devm_pinctrl_get(dev);
3475 if (!IS_ERR(hdmi->pinctrl)) {
3476 hdmi->unwedge_state =
3477 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3478 hdmi->default_state =
3479 pinctrl_lookup_state(hdmi->pinctrl, "default");
3481 if (IS_ERR(hdmi->default_state) ||
3482 IS_ERR(hdmi->unwedge_state)) {
3483 if (!IS_ERR(hdmi->unwedge_state))
3486 hdmi->default_state = NULL;
3487 hdmi->unwedge_state = NULL;
3491 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3492 if (IS_ERR(hdmi->ddc))
3493 hdmi->ddc = NULL;
3496 hdmi->bridge.driver_private = hdmi;
3497 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3498 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3500 hdmi->bridge.interlace_allowed = true;
3501 hdmi->bridge.ddc = hdmi->ddc;
3502 hdmi->bridge.of_node = pdev->dev.of_node;
3503 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
3505 if (hdmi->version >= 0x200a)
3506 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed;
3512 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3513 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3518 audio.phys = iores->start;
3519 audio.base = hdmi->regs;
3521 audio.hdmi = hdmi;
3523 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3524 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3526 pdevinfo.name = "dw-hdmi-ahb-audio";
3530 hdmi->audio = platform_device_register_full(&pdevinfo);
3534 audio.hdmi = hdmi;
3538 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3539 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3541 pdevinfo.name = "dw-hdmi-i2s-audio";
3545 hdmi->audio = platform_device_register_full(&pdevinfo);
3549 audio.phys = iores->start;
3550 audio.base = hdmi->regs;
3552 audio.hdmi = hdmi;
3555 hdmi->enable_audio = dw_hdmi_gp_audio_enable;
3556 hdmi->disable_audio = dw_hdmi_gp_audio_disable;
3558 pdevinfo.name = "dw-hdmi-gp-audio";
3563 hdmi->audio = platform_device_register_full(&pdevinfo);
3566 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
3567 cec.hdmi = hdmi;
3571 pdevinfo.name = "dw-hdmi-cec";
3576 hdmi->cec = platform_device_register_full(&pdevinfo);
3579 drm_bridge_add(&hdmi->bridge);
3581 return hdmi;
3584 i2c_put_adapter(hdmi->ddc);
3590 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3592 drm_bridge_remove(&hdmi->bridge);
3594 if (hdmi->audio && !IS_ERR(hdmi->audio))
3595 platform_device_unregister(hdmi->audio);
3596 if (!IS_ERR(hdmi->cec))
3597 platform_device_unregister(hdmi->cec);
3600 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3602 if (hdmi->i2c)
3603 i2c_del_adapter(&hdmi->i2c->adap);
3605 i2c_put_adapter(hdmi->ddc);
3609 /* -----------------------------------------------------------------------------
3616 struct dw_hdmi *hdmi;
3619 hdmi = dw_hdmi_probe(pdev, plat_data);
3620 if (IS_ERR(hdmi))
3621 return hdmi;
3623 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3625 dw_hdmi_remove(hdmi);
3629 return hdmi;
3633 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3635 dw_hdmi_remove(hdmi);
3639 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3641 dw_hdmi_init_hw(hdmi);
3646 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3647 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3649 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3651 MODULE_ALIAS("platform:dw-hdmi");