Lines Matching +full:hdmi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/phy/phy.h>
38 /* need to be unset if hdmi or i2c should control voltage */
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
62 * @lcdsel_big: reg value of selecting vop big for HDMI
63 * @lcdsel_lit: reg value of selecting vop little for HDMI
82 struct dw_hdmi *hdmi;
83 struct phy *phy;
199 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
201 struct device_node *np = hdmi->dev->of_node;
204 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
205 if (IS_ERR(hdmi->regmap)) {
206 dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
207 return PTR_ERR(hdmi->regmap);
210 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "ref");
211 if (!hdmi->ref_clk)
212 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "vpll");
214 if (IS_ERR(hdmi->ref_clk)) {
215 ret = PTR_ERR(hdmi->ref_clk);
216 if (ret != -EPROBE_DEFER)
217 dev_err(hdmi->dev, "failed to get reference clock\n");
221 hdmi->grf_clk = devm_clk_get_optional(hdmi->dev, "grf");
222 if (IS_ERR(hdmi->grf_clk)) {
223 ret = PTR_ERR(hdmi->grf_clk);
224 if (ret != -EPROBE_DEFER)
225 dev_err(hdmi->dev, "failed to get grf clock\n");
229 ret = devm_regulator_get_enable(hdmi->dev, "avdd-0v9");
233 ret = devm_regulator_get_enable(hdmi->dev, "avdd-1v8");
243 struct rockchip_hdmi *hdmi = data;
244 int pclk = mode->clock * 1000;
246 if (hdmi->chip_data->max_tmds_clock &&
247 mode->clock > hdmi->chip_data->max_tmds_clock)
250 if (hdmi->ref_clk) {
251 int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
253 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
257 if (hdmi->hdmiphy_clk) {
258 int rpclk = clk_round_rate(hdmi->hdmiphy_clk, pclk);
260 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
283 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
285 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
290 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
294 if (hdmi->chip_data->lcdsel_grf_reg < 0)
297 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
299 val = hdmi->chip_data->lcdsel_lit;
301 val = hdmi->chip_data->lcdsel_big;
303 ret = clk_prepare_enable(hdmi->grf_clk);
305 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
309 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
311 dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret);
313 clk_disable_unprepare(hdmi->grf_clk);
314 dev_dbg(hdmi->dev, "vop %s output to hdmi\n", ret ? "LIT" : "BIG");
324 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
325 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
342 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
346 return phy_power_on(hdmi->phy);
351 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
353 phy_power_off(hdmi->phy);
358 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
362 regmap_write(hdmi->regmap,
369 regmap_write(hdmi->regmap,
378 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
384 regmap_write(hdmi->regmap,
389 regmap_write(hdmi->regmap,
398 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
402 /* Enable and map pins to 3V grf-controlled io-voltage */
403 regmap_write(hdmi->regmap,
408 regmap_write(hdmi->regmap,
413 regmap_write(hdmi->regmap,
431 .lcdsel_grf_reg = -1,
467 .lcdsel_grf_reg = -1,
497 .lcdsel_grf_reg = -1,
511 { .compatible = "rockchip,rk3228-dw-hdmi",
514 { .compatible = "rockchip,rk3288-dw-hdmi",
517 { .compatible = "rockchip,rk3328-dw-hdmi",
520 { .compatible = "rockchip,rk3399-dw-hdmi",
523 { .compatible = "rockchip,rk3568-dw-hdmi",
538 struct rockchip_hdmi *hdmi;
541 if (!pdev->dev.of_node)
542 return -ENODEV;
544 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
545 if (!hdmi)
546 return -ENOMEM;
548 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
549 plat_data = devm_kmemdup(&pdev->dev, match->data,
552 return -ENOMEM;
554 hdmi->dev = &pdev->dev;
555 hdmi->plat_data = plat_data;
556 hdmi->chip_data = plat_data->phy_data;
557 plat_data->phy_data = hdmi;
558 plat_data->priv_data = hdmi;
559 encoder = &hdmi->encoder.encoder;
561 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
562 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
563 dev->of_node, 0, 0);
571 if (encoder->possible_crtcs == 0)
572 return -EPROBE_DEFER;
574 ret = rockchip_hdmi_parse_dt(hdmi);
576 if (ret != -EPROBE_DEFER)
577 dev_err(hdmi->dev, "Unable to parse OF data\n");
581 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
582 if (IS_ERR(hdmi->phy)) {
583 ret = PTR_ERR(hdmi->phy);
584 if (ret != -EPROBE_DEFER)
585 dev_err(hdmi->dev, "failed to get phy\n");
589 if (hdmi->phy) {
592 clkspec.np = hdmi->phy->dev.of_node;
593 hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec);
594 if (IS_ERR(hdmi->hdmiphy_clk))
595 hdmi->hdmiphy_clk = NULL;
598 if (hdmi->chip_data == &rk3568_chip_data) {
599 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
609 platform_set_drvdata(pdev, hdmi);
611 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
617 if (IS_ERR(hdmi->hdmi)) {
618 ret = PTR_ERR(hdmi->hdmi);
633 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
635 dw_hdmi_unbind(hdmi->hdmi);
636 drm_encoder_cleanup(&hdmi->encoder.encoder);
646 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
651 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
656 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
658 dw_hdmi_resume(hdmi->hdmi);
671 .name = "dwhdmi-rockchip",