/freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
H A D | hdmi.txt | 1 Qualcomm adreno/snapdragon hdmi output 4 - compatible: one of the following 5 * "qcom,hdmi-tx-8996" 6 * "qcom,hdmi-tx-8994" 7 * "qcom,hdmi-tx-8084" 8 * "qcom,hdmi-tx-8974" 9 * "qcom,hdmi-tx-8660" 10 * "qcom,hdmi-tx-8960" 11 - reg: Physical base address and length of the controller's registers 12 - reg-names: "core_physical" [all …]
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H A D | qcom,mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | amlogic,meson8-hdmi-tx-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY 10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 13 The HDMI TX PHY node should be the child of a syscon node with the 16 compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" 23 pattern: "^hdmi-phy@[0-9a-f]+$" 27 - items: [all …]
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H A D | mediatek,hdmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12 - Philipp Zabel <p.zabel@pengutronix.de> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel 17 output and drives the HDMI pads. [all …]
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H A D | phy-rockchip-inno-hdmi.txt | 1 ROCKCHIP HDMI PHY WITH INNO IP BLOCK 4 - compatible : should be one of the listed compatibles: 5 * "rockchip,rk3228-hdmi-phy", 6 * "rockchip,rk3328-hdmi-phy"; 7 - reg : Address and length of the hdmi phy control register set 8 - clocks : phandle + clock specifier for the phy clocks 9 - clock-names : string, clock name, must contain "sysclk" for system 10 control and register configuration, "refoclk" for crystal- 11 oscillator reference PLL clock input and "refpclk" for pclk- 13 - #clock-cells: should be 0. [all …]
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H A D | qcom,hdmi-phy-other.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Qualcomm Adreno/Snapdragon HDMI phy 11 - Rob Clark <robdclark@gmail.com> 16 - qcom,hdmi-phy-8660 17 - qcom,hdmi-phy-8960 18 - qcom,hdmi-phy-8974 19 - qcom,hdmi-phy-8084 [all …]
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H A D | qcom,hdmi-phy-qmp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Qualcomm Adreno/Snapdragon QMP HDMI phy 11 - Rob Clark <robdclark@gmail.com> 16 - qcom,hdmi-phy-8996 21 reg-names: 23 - const: hdmi_pll 24 - const: hdmi_tx_l0 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/exynos/ |
H A D | exynos_hdmi.txt | 1 Device-Tree bindings for drm hdmi driver 4 - compatible: value should be one among the following: 5 1) "samsung,exynos4210-hdmi" 6 2) "samsung,exynos4212-hdmi" 7 3) "samsung,exynos5420-hdmi" 8 4) "samsung,exynos5433-hdmi" 9 - reg: physical base address of the hdmi and length of memory mapped 11 - interrupts: interrupt number to the cpu. 12 - hpd-gpios: following information about the hotplug gpio pin. 16 - ddc: phandle to the hdmi ddc node [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/ |
H A D | allwinner,sun8i-a83t-hdmi-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A83t HDMI PHY 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 19 - allwinner,sun8i-a83t-hdmi-phy 20 - allwinner,sun8i-h3-hdmi-phy [all …]
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H A D | allwinner,sun8i-a83t-dw-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A83t DWC HDMI TX Encoder 10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller 11 IP with Allwinner\'s own PHY IP. It supports audio and video outputs 14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined 15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific 19 - Chen-Yu Tsai <wens@csie.org> [all …]
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H A D | amlogic,meson-dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller 11 - Neil Armstrong <neil.armstrong@linaro.org> 14 - $ref: /schemas/sound/dai-common.yaml# 18 - A Synopsys DesignWare HDMI Controller IP 19 - A TOP control block controlling the Clocks and PHY 20 - A custom HDMI PHY in order to convert video to TMDS signal [all …]
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H A D | brcm,bcm2711-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Broadcom BCM2711 HDMI Controller 10 - Eric Anholt <eric@anholt.net> 15 - brcm,bcm2711-hdmi0 16 - brcm,bcm2711-hdmi1 20 - description: HDMI controller register range 21 - description: DVP register range [all …]
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H A D | brcm,bcm-vc4.txt | 4 with HDMI output and the HVS (Hardware Video Scaler) for compositing 8 - compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4" 11 - compatible: Should be one of "brcm,bcm2835-pixelvalve0", 12 "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2" 13 - reg: Physical base address and length of the PV's registers 14 - interrupts: The interrupt number 15 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt 18 - compatible: Should be "brcm,bcm2835-hvs" 19 - reg: Physical base address and length of the HVS's registers 20 - interrupts: The interrupt number [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/samsung/ |
H A D | samsung,exynos-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung Exynos SoC HDMI 10 - Inki Dae <inki.dae@samsung.com> 11 - Seung-Woo Kim <sw0312.kim@samsung.com> 12 - Kyungmin Park <kyungmin.park@samsung.com> 13 - Krzysztof Kozlowski <krzk@kernel.org> 18 - samsung,exynos4210-hdmi [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/ |
H A D | mediatek,hdmi.txt | 1 Mediatek HDMI Encoder 4 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from 8 - compatible: Should be "mediatek,<chip>-hdmi". 9 - the supported chips are mt2701, mt7623 and mt8173 10 - reg: Physical base address and length of the controller's registers 11 - interrupts: The interrupt signal from the function block. 12 - clocks: device clocks 13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif". 15 - phys: phandle link to the HDMI PHY node. [all …]
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H A D | mediatek,hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Mediatek HDMI Encoder 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 14 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from 20 - mediatek,mt2701-hdmi 21 - mediatek,mt7623-hdmi [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/ |
H A D | dw_hdmi-rockchip.txt | 1 Rockchip DWC HDMI TX Encoder 4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 5 with a companion PHY IP. 7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in 9 following device-specific properties. 14 - compatible: should be one of the following: 15 "rockchip,rk3228-dw-hdmi" 16 "rockchip,rk3288-dw-hdmi" 17 "rockchip,rk3328-dw-hdmi" 18 "rockchip,rk3399-dw-hdmi" [all …]
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H A D | rockchip,dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip DWC HDMI TX Encoder 10 - Mark Yao <markyao0591@gmail.com> 13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 14 with a companion PHY IP. 17 - $ref: ../bridge/synopsys,dw-hdmi.yaml# 22 - rockchip,rk3228-dw-hdmi [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | qcom,mmcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jeffrey Hugo <quic_jhugo@quicinc.com> 11 - Taniy [all...] |
H A D | exynos5260-clock.txt | 4 independently from the device-tree. These clock controllers 11 dt-bindings/clock/exynos5260-clk.h header and can be used in 18 with following clock-output-names: 20 - "fin_pll" - PLL input clock from XXTI 21 - "xrtcxti" - input clock from XRTCXTI 22 - "ioclk_pcm_extclk" - pcm external operation clock 23 - "ioclk_spdif_extclk" - spdif external operation clock 24 - "ioclk_i2s_cdclk" - i2s0 codec clock 26 Phy clocks: 33 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 [all …]
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/ |
H A D | mt7623n.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright © 2017-2020 MediaTek Inc. 10 #include <dt-bindings/memory/mt2701-larb-port.h> 19 compatible = "mediatek,mt7623-g3dsys", 20 "mediatek,mt2701-g3dsys", 23 #clock-cell [all...] |
/freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
H A D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 8 -------- 11 - compatible: "ti,omap5-dss" 12 - reg: address and length of the register space 13 - ti,hwmods: "dss_core" 14 - clocks: handle to fclk 15 - clock-names: "fck" 18 - DISPC 21 - DSS Submodules: RFBI, DSI, HDMI 22 - Video port for DPI output [all …]
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H A D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic 8 -------- 11 - compatible: "ti,omap4-dss" 12 - reg: address and length of the register space 13 - ti,hwmods: "dss_core" 14 - clocks: handle to fclk 15 - clock-names: "fck" 18 - DISPC 21 - DSS Submodules: RFBI, VENC, DSI, HDMI 22 - Video port for DPI output [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/allwinner/ |
H A D | sun50i-a64-sopine-baseboard.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 // Based on sun50i-a64-pine64.dts, which is: 6 /dts-v1/; 8 #include "sun50i-a64-sopine.dtsi" 12 compatible = "pine64,sopine-baseboard", "pine64,sopine", 13 "allwinner,sun50i-a64"; 25 stdout-path = "serial0:115200n8"; 28 hdmi-connector { 29 compatible = "hdmi-connector"; 34 remote-endpoint = <&hdmi_out_con>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/soc/imx/ |
H A D | fsl,imx8mp-hdmi-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MP HDMI blk-ctrl 10 - Lucas Stach <l.stach@pengutronix.de> 13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to 15 peripherals located in the HDMI domain of the SoC. 20 - const: fsl,imx8mp-hdmi-blk-ctrl 21 - const: syscon [all …]
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