Lines Matching +full:hdmi +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
47 power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
52 compatible = "mediatek,mt7623-mmsys",
53 "mediatek,mt2701-mmsys",
56 #clock-cells = <1>;
60 compatible = "mediatek,mt7623-smi-larb",
61 "mediatek,mt2701-smi-larb";
64 mediatek,larb-id = <0>;
67 clock-names = "apb", "smi";
68 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
72 compatible = "mediatek,mt7623-smi-larb",
73 "mediatek,mt2701-smi-larb";
76 mediatek,larb-id = <1>;
79 clock-names = "apb", "smi";
80 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
84 compatible = "mediatek,mt7623-smi-larb",
85 "mediatek,mt2701-smi-larb";
88 mediatek,larb-id = <2>;
91 clock-names = "apb", "smi";
92 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
96 compatible = "mediatek,mt7623-imgsys",
97 "mediatek,mt2701-imgsys",
100 #clock-cells = <1>;
104 compatible = "mediatek,mt7623-m4u",
105 "mediatek,mt2701-m4u";
109 clock-names = "bclk";
111 #iommu-cells = <1>;
115 compatible = "mediatek,mt7623-jpgdec",
116 "mediatek,mt2701-jpgdec";
121 clock-names = "jpgdec-smi",
123 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
129 compatible = "mediatek,mt7623-smi-common",
130 "mediatek,mt2701-smi-common";
135 clock-names = "apb", "smi", "async";
136 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
140 compatible = "mediatek,mt7623-disp-ovl",
141 "mediatek,mt2701-disp-ovl";
149 compatible = "mediatek,mt7623-disp-rdma",
150 "mediatek,mt2701-disp-rdma";
158 compatible = "mediatek,mt7623-disp-wdma",
159 "mediatek,mt2701-disp-wdma";
167 compatible = "mediatek,mt7623-disp-pwm",
168 "mediatek,mt2701-disp-pwm";
170 #pwm-cells = <2>;
173 clock-names = "main", "mm";
178 compatible = "mediatek,mt7623-disp-color",
179 "mediatek,mt2701-disp-color";
186 compatible = "mediatek,mt7623-dsi",
187 "mediatek,mt2701-dsi";
193 clock-names = "engine", "digital", "hs";
195 phy-names = "dphy";
200 compatible = "mediatek,mt7623-disp-mutex",
201 "mediatek,mt2701-disp-mutex";
208 compatible = "mediatek,mt7623-disp-rdma",
209 "mediatek,mt2701-disp-rdma";
217 compatible = "mediatek,mt7623-dpi",
218 "mediatek,mt2701-dpi";
224 clock-names = "pixel", "engine", "pll";
228 hdmi0: hdmi@14015000 {
229 compatible = "mediatek,mt7623-hdmi",
230 "mediatek,mt2701-hdmi";
236 clock-names = "pixel", "pll", "bclk", "spdif";
238 phy-names = "hdmi";
239 mediatek,syscon-hdmi = <&mmsys 0x900>;
244 mipi_tx0: dsi-phy@10010000 {
245 compatible = "mediatek,mt7623-mipi-tx",
246 "mediatek,mt2701-mipi-tx";
249 clock-output-names = "mipi_tx0_pll";
250 #clock-cells = <0>;
251 #phy-cells = <0>;
255 compatible = "mediatek,mt7623-cec",
256 "mediatek,mt8173-cec";
263 hdmi_phy: hdmi-phy@10209100 {
264 compatible = "mediatek,mt7623-hdmi-phy",
265 "mediatek,mt2701-hdmi-phy";
268 clock-names = "pll_ref";
269 clock-output-names = "hdmitx_dig_cts";
270 #clock-cells = <0>;
271 #phy-cells = <0>;
276 compatible = "mediatek,mt7623-hdmi-ddc",
277 "mediatek,mt8173-hdmi-ddc";
281 clock-names = "ddc-i2c";
287 hdmi_pins_a: hdmi-default {
288 pins-hdmi {
290 input-enable;
291 bias-pull-down;
295 hdmi_ddc_pins_a: hdmi_ddc-default {
296 pins-hdmi-ddc {