Lines Matching +full:hdmi +full:- +full:phy

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek HDMI Encoder
10   - CK Hu <ck.hu@mediatek.com>
11   - Jitao shi <jitao.shi@mediatek.com>
14   The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
20       - mediatek,mt2701-hdmi
21       - mediatek,mt7623-hdmi
22       - mediatek,mt8167-hdmi
23       - mediatek,mt8173-hdmi
33       - description: Pixel Clock
34       - description: HDMI PLL
35       - description: Bit Clock
36       - description: S/PDIF Clock
38   clock-names:
40       - const: pixel
41       - const: pll
42       - const: bclk
43       - const: spdif
48   phy-names:
50       - const: hdmi
52   mediatek,syscon-hdmi:
53     $ref: /schemas/types.yaml#/definitions/phandle-array
55       - items:
56           - description: phandle to system configuration registers
57           - description: register offset in the system configuration registers
74           node that contains a ddc-i2c-bus property, or to the  input port of an attached
78       - port@0
79       - port@1
82   - compatible
83   - reg
84   - interrupts
85   - clocks
86   - clock-names
87   - phys
88   - phy-names
89   - mediatek,syscon-hdmi
90   - ports
95   - |
96     #include <dt-bindings/clock/mt8173-clk.h>
97     #include <dt-bindings/interrupt-controller/arm-gic.h>
98     #include <dt-bindings/interrupt-controller/irq.h>
99     hdmi0: hdmi@14025000 {
100         compatible = "mediatek,mt8173-hdmi";
107         clock-names = "pixel", "pll", "bclk", "spdif";
108         pinctrl-names = "default";
109         pinctrl-0 = <&hdmi_pin>;
111         phy-names = "hdmi";
112         mediatek,syscon-hdmi = <&mmsys 0x900>;
115           #address-cells = <1>;
116           #size-cells = <0>;
122               remote-endpoint = <&dpi0_out>;
130               remote-endpoint = <&hdmi_con_in>;