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/linux/sound/arm/
H A Daaci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
19 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
20 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
41 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
43 #define AACI_DR1 0x090 /* data read/written fifo 1 */
44 #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
45 #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
46 #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
49 * TX/RX fifo control register (CR). P48
[all …]
/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SIFCTR 0x30 /* FIFO Control Register */
22 #define SITFDR 0x50 /* Transmit FIFO Data Register */
25 #define SIRFDR 0x60 /* Receive FIFO Data Register */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
37 #define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
38 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
46 #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */
47 #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */
48 #define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */
[all …]
/linux/drivers/gpib/include/
H A Dtnt4882_registers.h1 /* SPDX-License-Identifier: GPL-2.0 */
49 /* TURBO-488 registers bit definitions */
62 /* CFG -- Configuration Register (write only) */
65 * (tnt4882 one-chip and newer only?)
69 TNT_A_B = (1 << 4), /* order to use fifos 1=fifo A first(big endian),
70 * 0=fifo b first(little endian)
75 TNT_B_16BIT = (1 << 0), /* 1=FIFO is 16-bit register, 0=8-bit */
78 /* CMDR -- Command Register */
89 /* HSSEL -- handshake select register (write only) */
96 /* IMR0 -- Interrupt Mode Register 0 */
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dcirrus,ep7209-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Shiyan <shc_work@mail.ru>
17 ---------------------------
28 12: UTXINT1 UART1 transmit FIFO half empty
29 13: URXINT1 UART1 receive FIFO half full
33 17: SS2RX SSI2 receive FIFO half or greater full
34 18: SS2TX SSI2 transmit FIFO less than half empty
[all …]
/linux/drivers/tty/hvc/
H A Dhvc_dcc.c1 // SPDX-License-Identifier: GPL-2.0
26 /* Lock to serialize access to DCC fifo */
42 struct earlycon_device *dev = con->data; in dcc_early_write()
44 uart_console_write(&dev->port, s, n, dcc_uart_console_putchar); in dcc_early_write()
52 while (--count && (__dcc_getstatus() & DCC_STATUS_TX)) in dcc_early_console_setup()
56 return -ENODEV; in dcc_early_console_setup()
58 device->con->write = dcc_early_write; in dcc_early_console_setup()
129 * Workqueue function that writes the output FIFO to the DCC on core 0.
138 /* While there's data in the output FIFO, write it to the DCC */ in dcc_put_work()
156 * input FIFO.
[all …]
/linux/drivers/tty/serial/
H A Datmel_serial.h1 /* SPDX-License-Identifier: GPL-2.0+ */
27 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
31 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
36 #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
37 #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
38 #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
39 #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
40 #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
81 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
99 #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
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H A Dvt8500_serial.c1 // SPDX-License-Identifier: GPL-2.0
39 #define VT8500_URFCR 0x0020 /* FIFO control */
40 #define VT8500_URFIDX 0x0024 /* FIFO index */
43 #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
44 #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
50 #define TXDE (1 << 0) /* Tx Data empty */
52 #define TXFAE (1 << 2) /* Tx FIFO almost empty */
53 #define TXFE (1 << 3) /* Tx FIFO empty */
54 #define RXFAF (1 << 4) /* Rx FIFO almost full */
55 #define RXFF (1 << 5) /* Rx FIFO full */
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/linux/drivers/sbus/char/
H A Ductrl.c1 // SPDX-License-Identifier: GPL-2.0-only
56 #define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */
57 #define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */
58 #define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */
59 #define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */
60 #define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */
61 #define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */
62 #define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */
63 #define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */
66 #define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */
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/linux/include/uapi/linux/
H A Dserial_reg.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
38 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
47 #define UART_IIR_64BYTE_FIFO 0x20 /* 16750 64 bytes FIFO */
49 #define UART_IIR_FIFO_ENABLED_8250 0x00 /* 8250: no FIFO */
50 #define UART_IIR_FIFO_ENABLED_16550 0x80 /* 16550: (broken/unusable) FIFO */
51 #define UART_IIR_FIFO_ENABLED_16550A 0xc0 /* 16550A: FIFO enabled */
52 #define UART_IIR_FIFO_ENABLED_16750 0xe0 /* 16750: 64 bytes FIFO enabled */
54 #define UART_FCR 2 /* Out: FIFO Control Register */
55 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
56 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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/linux/drivers/scsi/
H A Dfdomain.h1 /* SPDX-License-Identifier: GPL-2.0 */
40 #define ASTAT_FIFODIR BIT(4) /* FIFO direction */
41 #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
45 #define ICTL_FIFO_MASK 0x0f /* FIFO threshold, 1/16 FIFO size */
46 #define ICTL_FIFO BIT(4) /* Int. on FIFO count */
50 #define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
51 #define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
52 #define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */
53 #define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */
54 #define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */
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/linux/drivers/memstick/host/
H A Dr592.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2010 - Maxim Levitsky
19 #define R592_TPC_EXEC_BIG_FIFO (1 << 26) /* If bit 26 is set, large fifo is used (reg 48) */
23 /* Window for small TPC fifo (big endian)*/
25 /* Not used in driver, because large fifo does better job */
29 /* Status register (ms int, small fifo, IO)*/
37 /* Fifo status */
38 #define R592_STATUS_SFIFO_FULL (1 << 20) /* Small Fifo almost full (last chunk is written) */
39 #define R592_STATUS_SFIFO_EMPTY (1 << 21) /* Small Fifo empty */
48 #define R592_STATUS_SFIFO_INPUT (1 << 30) /* Small fifo received data*/
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/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-tef.c1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
36 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFUA, &tef_ua); in mcp251xfd_tef_tail_get_from_chip()
59 netdev_err(priv->ndev, in mcp251xfd_check_tef_tail()
62 return -EILSEQ; in mcp251xfd_check_tef_tail()
73 struct net_device_stats *stats = &priv->ndev->stats; in mcp251xfd_handle_tefif_one()
81 hw_tef_obj->flags); in mcp251xfd_handle_tefif_one()
82 tef_tail_masked = priv->tef->tail & in mcp251xfd_handle_tefif_one()
86 * bits of a FIFOSTA register, here the TX FIFO tail index in mcp251xfd_handle_tefif_one()
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_self_test.c1 // SPDX-License-Identifier: GPL-2.0
30 u32 imm1; /* 1st value in predicate condition, left-to-right */
31 u32 imm2; /* 2nd value in predicate condition, left-to-right */
32 u32 imm3; /* 3rd value in predicate condition, left-to-right */
33 u32 imm4; /* 4th value in predicate condition, left-to-right */
36 /* struct representing self test record - a single test */
54 return (args->val1 == args->imm1); in peq()
59 return (args->val1 != args->imm1); in pneq()
64 return ((args->val1 & args->imm1) != args->imm2); in pand_neq()
69 return (((args->val1 & args->imm1) != args->imm2) && in pand_neq_x2()
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/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be one of:
18 "xlnx,axi-fifo-mm-s-4.1"
19 "xlnx,axi-fifo-mm-s-4.2"
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/linux/drivers/parport/
H A Dparport_ip32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Low-level parallel port routines for built-in port on SGI IP32
10 * Thanks to Ilya A. Volynets-Evenbakh for his help.
21 * SPP/ECP FIFO can be driven in PIO or DMA mode. PIO mode can work with
32 * If DMA mode works well, decide if support for PIO FIFO modes should be
35 * the linux-mips.org tree. Note: the MIPS specific functions readsb()
40 /* The built-in parallel port on the SGI 02 workstation (a.k.a. IP32) is an
43 * FIFO buffer and supports DMA transfers.
49 * registers are port-mapped. On the O2, they are memory-mapped.
51 * it is for the built-in serial ports on the same chip).
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/linux/arch/sh/include/asm/
H A Dsmc37c93x.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * linux/include/asm-sh/smc37c93x.h
61 #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
97 #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
109 /* FIFO Control Register */
111 #define FCR_FEN 0x0100 /* FIFO enable */
112 #define FCR_RFRES 0x0200 /* Receiver FIFO reset */
113 #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
144 #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
145 #define LSR_TEMT 0x4000 /* Transmitter Empty */
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/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
78 /* Channel FIFO definition */
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
129 u32 full, u32 empty) in sprd_mcdt_dac_set_watermark() argument
133 (empty << MCDT_CH_FIFO_AE_SHIFT) & MCDT_CH_FIFO_AE_MASK; in sprd_mcdt_dac_set_watermark()
141 u32 full, u32 empty) in sprd_mcdt_adc_set_watermark() argument
[all...]
/linux/sound/soc/cirrus/
H A Dep93xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/soc/ep93xx-i2s.c
29 #include "ep93xx-pcm.h"
58 * Transmit empty interrupt level select:
59 * 0 - Generate interrupt when FIFO is half empty
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/linux/io_uring/
H A Dmpscq.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * mpscq - lockless multi-producer, single-consumer FIFO queue
16 * instead of an unconditional push, keeping tail == stub a reliable empty test
19 * Producers may run in any context (task, softirq, hardirq) and are wait-free:
20 * a push is one xchg() plus one store, with no retry loops. FIFO order between
21 * producers is the order in which the xchg() on ->tail serializes them.
23 * The price for linked-list FIFO is that a push publishes the node in two
27 * reports false. The consumer must not treat such a NULL as "queue empty" - it
42 * every pop, and having it share a line with ->tail would have the consumer
47 q->tail = *headp = &q->stub; in mpscq_init()
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
96 #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
98 #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
101 #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */
118 #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
119 #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */
140 /* Receive Almost Empty Threshold */
[all …]
/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
33 #define FCR 2 // ! Fifo Control Register (Write)
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
69 #define FCR_RXCLR 0x02 // Reset Rx FIFO
70 #define FCR_TXCLR 0x04 // Reset Tx FIFO
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx.seq4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
51 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
58 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
100 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
124 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
128 * and re-selections. Make the LED status
159 * pending select-outs.
169 * Since this status did not consume a FIFO, we have to
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/linux/arch/arm/include/debug/
H A Dzynq.S1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
11 #define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
12 #define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
50 bne 1002b @ wait if FIFO is full
/linux/drivers/mailbox/
H A Dcix-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
23 * [9]fifo base channel
103 * For the REG and FIFO types of transfers, the message format is as follows:
117 if (priv->use_shmem) in cix_mbox_write()
118 iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_write()
120 iowrite32(val, priv->base + offset); in cix_mbox_write()
125 if (priv->use_shmem) in cix_mbox_read()
126 return ioread32(priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_read()
128 return ioread32(priv->base + offset); in cix_mbox_read()
133 struct cix_mbox_priv *priv = to_cix_mbox_priv(chan->mbox); in mbox_fifo_empty()
[all …]
/linux/sound/soc/pxa/
H A Dpxa2xx-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx-i2s.c -- ALSA Soc Audio Layer
23 #include <linux/platform_data/asoc-pxa.h>
25 #include "pxa2xx-li
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