1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2cb5a6ffcSRussell King /* 3cb5a6ffcSRussell King * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver 4cb5a6ffcSRussell King * 5cb5a6ffcSRussell King * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6cb5a6ffcSRussell King */ 7cb5a6ffcSRussell King #ifndef AACI_H 8cb5a6ffcSRussell King #define AACI_H 9cb5a6ffcSRussell King 10cb5a6ffcSRussell King /* 11cb5a6ffcSRussell King * Control and status register offsets 12cb5a6ffcSRussell King * P39. 13cb5a6ffcSRussell King */ 14cb5a6ffcSRussell King #define AACI_CSCH1 0x000 15cb5a6ffcSRussell King #define AACI_CSCH2 0x014 16cb5a6ffcSRussell King #define AACI_CSCH3 0x028 17cb5a6ffcSRussell King #define AACI_CSCH4 0x03c 18cb5a6ffcSRussell King 19cb5a6ffcSRussell King #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */ 20cb5a6ffcSRussell King #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */ 21cb5a6ffcSRussell King #define AACI_SR 0x008 /* 12 bits Status */ 22cb5a6ffcSRussell King #define AACI_ISR 0x00c /* 7 bits Int Status */ 23cb5a6ffcSRussell King #define AACI_IE 0x010 /* 7 bits Int Enable */ 24cb5a6ffcSRussell King 25cb5a6ffcSRussell King /* 26cb5a6ffcSRussell King * Other registers 27cb5a6ffcSRussell King */ 28cb5a6ffcSRussell King #define AACI_SL1RX 0x050 29cb5a6ffcSRussell King #define AACI_SL1TX 0x054 30cb5a6ffcSRussell King #define AACI_SL2RX 0x058 31cb5a6ffcSRussell King #define AACI_SL2TX 0x05c 32cb5a6ffcSRussell King #define AACI_SL12RX 0x060 33cb5a6ffcSRussell King #define AACI_SL12TX 0x064 34cb5a6ffcSRussell King #define AACI_SLFR 0x068 /* slot flags */ 35cb5a6ffcSRussell King #define AACI_SLISTAT 0x06c /* slot interrupt status */ 36cb5a6ffcSRussell King #define AACI_SLIEN 0x070 /* slot interrupt enable */ 37cb5a6ffcSRussell King #define AACI_INTCLR 0x074 /* interrupt clear */ 38cb5a6ffcSRussell King #define AACI_MAINCR 0x078 /* main control */ 39cb5a6ffcSRussell King #define AACI_RESET 0x07c /* reset control */ 40cb5a6ffcSRussell King #define AACI_SYNC 0x080 /* sync control */ 41cb5a6ffcSRussell King #define AACI_ALLINTS 0x084 /* all fifo interrupt status */ 42cb5a6ffcSRussell King #define AACI_MAINFR 0x088 /* main flag register */ 43cb5a6ffcSRussell King #define AACI_DR1 0x090 /* data read/written fifo 1 */ 44cb5a6ffcSRussell King #define AACI_DR2 0x0b0 /* data read/written fifo 2 */ 45cb5a6ffcSRussell King #define AACI_DR3 0x0d0 /* data read/written fifo 3 */ 46cb5a6ffcSRussell King #define AACI_DR4 0x0f0 /* data read/written fifo 4 */ 47cb5a6ffcSRussell King 48cb5a6ffcSRussell King /* 4941762b8cSKevin Hilman * TX/RX fifo control register (CR). P48 50cb5a6ffcSRussell King */ 5141762b8cSKevin Hilman #define CR_FEN (1 << 16) /* fifo enable */ 5241762b8cSKevin Hilman #define CR_COMPACT (1 << 15) /* compact mode */ 5341762b8cSKevin Hilman #define CR_SZ16 (0 << 13) /* 16 bits */ 5441762b8cSKevin Hilman #define CR_SZ18 (1 << 13) /* 18 bits */ 5541762b8cSKevin Hilman #define CR_SZ20 (2 << 13) /* 20 bits */ 5641762b8cSKevin Hilman #define CR_SZ12 (3 << 13) /* 12 bits */ 5741762b8cSKevin Hilman #define CR_SL12 (1 << 12) 5841762b8cSKevin Hilman #define CR_SL11 (1 << 11) 5941762b8cSKevin Hilman #define CR_SL10 (1 << 10) 6041762b8cSKevin Hilman #define CR_SL9 (1 << 9) 6141762b8cSKevin Hilman #define CR_SL8 (1 << 8) 6241762b8cSKevin Hilman #define CR_SL7 (1 << 7) 6341762b8cSKevin Hilman #define CR_SL6 (1 << 6) 6441762b8cSKevin Hilman #define CR_SL5 (1 << 5) 6541762b8cSKevin Hilman #define CR_SL4 (1 << 4) 6641762b8cSKevin Hilman #define CR_SL3 (1 << 3) 6741762b8cSKevin Hilman #define CR_SL2 (1 << 2) 6841762b8cSKevin Hilman #define CR_SL1 (1 << 1) 6941762b8cSKevin Hilman #define CR_EN (1 << 0) /* transmit enable */ 70cb5a6ffcSRussell King 71cb5a6ffcSRussell King /* 72cb5a6ffcSRussell King * status register bits. P49 73cb5a6ffcSRussell King */ 74cb5a6ffcSRussell King #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */ 75cb5a6ffcSRussell King #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */ 76cb5a6ffcSRussell King #define SR_TXU (1 << 9) /* tx underrun */ 77cb5a6ffcSRussell King #define SR_RXO (1 << 8) /* rx overrun */ 78cb5a6ffcSRussell King #define SR_TXB (1 << 7) /* tx busy */ 79cb5a6ffcSRussell King #define SR_RXB (1 << 6) /* rx busy */ 80cb5a6ffcSRussell King #define SR_TXFF (1 << 5) /* tx fifo full */ 81cb5a6ffcSRussell King #define SR_RXFF (1 << 4) /* rx fifo full */ 82cb5a6ffcSRussell King #define SR_TXHE (1 << 3) /* tx fifo half empty */ 83cb5a6ffcSRussell King #define SR_RXHF (1 << 2) /* rx fifo half full */ 84cb5a6ffcSRussell King #define SR_TXFE (1 << 1) /* tx fifo empty */ 85cb5a6ffcSRussell King #define SR_RXFE (1 << 0) /* rx fifo empty */ 86cb5a6ffcSRussell King 87cb5a6ffcSRussell King /* 88cb5a6ffcSRussell King * interrupt status register bits. 89cb5a6ffcSRussell King */ 90cb5a6ffcSRussell King #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */ 91cb5a6ffcSRussell King #define ISR_URINTR (1 << 5) /* tx underflow */ 92cb5a6ffcSRussell King #define ISR_ORINTR (1 << 4) /* rx overflow */ 93cb5a6ffcSRussell King #define ISR_RXINTR (1 << 3) /* rx fifo */ 94cb5a6ffcSRussell King #define ISR_TXINTR (1 << 2) /* tx fifo intr */ 95cb5a6ffcSRussell King #define ISR_RXTOINTR (1 << 1) /* tx timeout */ 96cb5a6ffcSRussell King #define ISR_TXCINTR (1 << 0) /* tx complete */ 97cb5a6ffcSRussell King 98cb5a6ffcSRussell King /* 99cb5a6ffcSRussell King * interrupt enable register bits. 100cb5a6ffcSRussell King */ 101cb5a6ffcSRussell King #define IE_RXTOIE (1 << 6) 102cb5a6ffcSRussell King #define IE_URIE (1 << 5) 103cb5a6ffcSRussell King #define IE_ORIE (1 << 4) 104cb5a6ffcSRussell King #define IE_RXIE (1 << 3) 105cb5a6ffcSRussell King #define IE_TXIE (1 << 2) 106cb5a6ffcSRussell King #define IE_RXTIE (1 << 1) 107cb5a6ffcSRussell King #define IE_TXCIE (1 << 0) 108cb5a6ffcSRussell King 109cb5a6ffcSRussell King /* 110cb5a6ffcSRussell King * interrupt status. P51 111cb5a6ffcSRussell King */ 112cb5a6ffcSRussell King #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */ 113cb5a6ffcSRussell King #define ISR_UR (1 << 5) /* tx fifo underrun */ 114cb5a6ffcSRussell King #define ISR_OR (1 << 4) /* rx fifo overrun */ 115cb5a6ffcSRussell King #define ISR_RX (1 << 3) /* rx interrupt status */ 116cb5a6ffcSRussell King #define ISR_TX (1 << 2) /* tx interrupt status */ 117cb5a6ffcSRussell King #define ISR_RXTO (1 << 1) /* rx timeout */ 118cb5a6ffcSRussell King #define ISR_TXC (1 << 0) /* tx complete */ 119cb5a6ffcSRussell King 120cb5a6ffcSRussell King /* 121cb5a6ffcSRussell King * interrupt enable. P52 122cb5a6ffcSRussell King */ 123cb5a6ffcSRussell King #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */ 124cb5a6ffcSRussell King #define IE_UR (1 << 5) /* tx fifo underrun */ 125cb5a6ffcSRussell King #define IE_OR (1 << 4) /* rx fifo overrun */ 126cb5a6ffcSRussell King #define IE_RX (1 << 3) /* rx interrupt status */ 127cb5a6ffcSRussell King #define IE_TX (1 << 2) /* tx interrupt status */ 128cb5a6ffcSRussell King #define IE_RXTO (1 << 1) /* rx timeout */ 129cb5a6ffcSRussell King #define IE_TXC (1 << 0) /* tx complete */ 130cb5a6ffcSRussell King 131cb5a6ffcSRussell King /* 132cb5a6ffcSRussell King * slot flag register bits. P56 133cb5a6ffcSRussell King */ 134cb5a6ffcSRussell King #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */ 135cb5a6ffcSRussell King #define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */ 136cb5a6ffcSRussell King #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */ 137cb5a6ffcSRussell King #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */ 138cb5a6ffcSRussell King #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */ 139cb5a6ffcSRussell King #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */ 140cb5a6ffcSRussell King #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */ 141cb5a6ffcSRussell King #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */ 142cb5a6ffcSRussell King #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */ 143cb5a6ffcSRussell King #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */ 144cb5a6ffcSRussell King #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */ 145cb5a6ffcSRussell King #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */ 146cb5a6ffcSRussell King #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */ 147cb5a6ffcSRussell King #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */ 148cb5a6ffcSRussell King 149cb5a6ffcSRussell King /* 150cb5a6ffcSRussell King * Interrupt clear register. 151cb5a6ffcSRussell King */ 152cb5a6ffcSRussell King #define ICLR_RXTOFEC4 (1 << 12) 153cb5a6ffcSRussell King #define ICLR_RXTOFEC3 (1 << 11) 154cb5a6ffcSRussell King #define ICLR_RXTOFEC2 (1 << 10) 155cb5a6ffcSRussell King #define ICLR_RXTOFEC1 (1 << 9) 156cb5a6ffcSRussell King #define ICLR_TXUEC4 (1 << 8) 157cb5a6ffcSRussell King #define ICLR_TXUEC3 (1 << 7) 158cb5a6ffcSRussell King #define ICLR_TXUEC2 (1 << 6) 159cb5a6ffcSRussell King #define ICLR_TXUEC1 (1 << 5) 160cb5a6ffcSRussell King #define ICLR_RXOEC4 (1 << 4) 161cb5a6ffcSRussell King #define ICLR_RXOEC3 (1 << 3) 162cb5a6ffcSRussell King #define ICLR_RXOEC2 (1 << 2) 163cb5a6ffcSRussell King #define ICLR_RXOEC1 (1 << 1) 164cb5a6ffcSRussell King #define ICLR_WISC (1 << 0) 165cb5a6ffcSRussell King 166cb5a6ffcSRussell King /* 167cb5a6ffcSRussell King * Main control register bits. P62 168cb5a6ffcSRussell King */ 169cb5a6ffcSRussell King #define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */ 170cb5a6ffcSRussell King #define MAINCR_DMAEN (1 << 9) /* dma enable */ 171cb5a6ffcSRussell King #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */ 172cb5a6ffcSRussell King #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */ 173cb5a6ffcSRussell King #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */ 174cb5a6ffcSRussell King #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */ 175cb5a6ffcSRussell King #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */ 176cb5a6ffcSRussell King #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */ 177cb5a6ffcSRussell King #define MAINCR_LPM (1 << 2) /* low power mode */ 178cb5a6ffcSRussell King #define MAINCR_LOOPBK (1 << 1) /* loopback */ 179cb5a6ffcSRussell King #define MAINCR_IE (1 << 0) /* aaci interface enable */ 180cb5a6ffcSRussell King 181cb5a6ffcSRussell King /* 182cb5a6ffcSRussell King * Reset register bits. P65 183cb5a6ffcSRussell King */ 184cb5a6ffcSRussell King #define RESET_NRST (1 << 0) 185cb5a6ffcSRussell King 186cb5a6ffcSRussell King /* 187cb5a6ffcSRussell King * Sync register bits. P65 188cb5a6ffcSRussell King */ 189cb5a6ffcSRussell King #define SYNC_FORCE (1 << 0) 190cb5a6ffcSRussell King 191cb5a6ffcSRussell King /* 192cb5a6ffcSRussell King * Main flag register bits. P66 193cb5a6ffcSRussell King */ 194cb5a6ffcSRussell King #define MAINFR_TXB (1 << 1) /* transmit busy */ 195cb5a6ffcSRussell King #define MAINFR_RXB (1 << 0) /* receive busy */ 196cb5a6ffcSRussell King 197cb5a6ffcSRussell King 198cb5a6ffcSRussell King 199cb5a6ffcSRussell King struct aaci_runtime { 200e12ba644Sviro@ZenIV.linux.org.uk void __iomem *base; 201e12ba644Sviro@ZenIV.linux.org.uk void __iomem *fifo; 202d6a89fefSRussell King spinlock_t lock; 203cb5a6ffcSRussell King 204cb5a6ffcSRussell King struct ac97_pcm *pcm; 205cb5a6ffcSRussell King int pcm_open; 206cb5a6ffcSRussell King 207cb5a6ffcSRussell King u32 cr; 208ceb9e476STakashi Iwai struct snd_pcm_substream *substream; 209cb5a6ffcSRussell King 210c0dea82cSRussell King unsigned int period; /* byte size of a "period" */ 211c0dea82cSRussell King 212cb5a6ffcSRussell King /* 213cb5a6ffcSRussell King * PIO support 214cb5a6ffcSRussell King */ 215cb5a6ffcSRussell King void *start; 216cb5a6ffcSRussell King void *end; 217cb5a6ffcSRussell King void *ptr; 218cb5a6ffcSRussell King int bytes; 2195d350cbaSRussell King unsigned int fifo_bytes; 220cb5a6ffcSRussell King }; 221cb5a6ffcSRussell King 222cb5a6ffcSRussell King struct aaci { 223cb5a6ffcSRussell King struct amba_device *dev; 224ceb9e476STakashi Iwai struct snd_card *card; 225e12ba644Sviro@ZenIV.linux.org.uk void __iomem *base; 2265d350cbaSRussell King unsigned int fifo_depth; 227b60fb519SRussell King unsigned int users; 228b60fb519SRussell King struct mutex irq_lock; 229cb5a6ffcSRussell King 230cb5a6ffcSRussell King /* AC'97 */ 23112aa7579SIngo Molnar struct mutex ac97_sem; 232a5f65029SAndrew Morton struct snd_ac97_bus *ac97_bus; 23359b8175cSLinus Torvalds struct snd_ac97 *ac97; 234cb5a6ffcSRussell King 235cb5a6ffcSRussell King u32 maincr; 236cb5a6ffcSRussell King 237cb5a6ffcSRussell King struct aaci_runtime playback; 238cb5a6ffcSRussell King struct aaci_runtime capture; 239cb5a6ffcSRussell King 240ceb9e476STakashi Iwai struct snd_pcm *pcm; 241cb5a6ffcSRussell King }; 242cb5a6ffcSRussell King 243cb5a6ffcSRussell King #define ACSTREAM_FRONT 0 244cb5a6ffcSRussell King #define ACSTREAM_SURROUND 1 245cb5a6ffcSRussell King #define ACSTREAM_LFE 2 246cb5a6ffcSRussell King 247cb5a6ffcSRussell King #endif 248