Home
last modified time | relevance | path

Searched full:cru (Results 1 – 25 of 288) sorted by relevance

12345678910>>...12

/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-video.c3 * Driver for Renesas RZ/G2L CRU
21 #include "rzg2l-cru.h"
23 /* HW CRU Registers Definition */
25 /* CRU Control Register */
29 /* CRU Interrupt Enable Register */
33 /* CRU Interrupt Status Register */
37 /* CRU Reset Register */
41 /* Memory Bank Base Address (Lower) Register for CRU Image Data */
44 /* Memory Bank Base Address (Higher) Register for CRU Image Data */
47 /* Memory Bank Enable Register for CRU Image Data */
[all …]
H A Drzg2l-core.c3 * Driver for Renesas RZ/G2L CRU
24 #include "rzg2l-cru.h"
41 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); in rzg2l_cru_group_notify_complete() local
45 ret = rzg2l_cru_ip_subdev_register(cru); in rzg2l_cru_group_notify_complete()
49 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete()
51 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete()
55 ret = rzg2l_cru_video_register(cru); in rzg2l_cru_group_notify_complete()
60 * CRU can be connected either to CSI2 or PARALLEL device in rzg2l_cru_group_notify_complete()
63 * Create media device link between CSI-2 <-> CRU IP in rzg2l_cru_group_notify_complete()
65 source = &cru->csi.subdev->entity; in rzg2l_cru_group_notify_complete()
[all …]
H A Drzg2l-ip.c3 * Driver for Renesas RZ/G2L CRU
9 #include "rzg2l-cru.h"
37 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) in rzg2l_cru_ip_get_src_fmt() argument
42 state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); in rzg2l_cru_ip_get_src_fmt()
51 struct rzg2l_cru_dev *cru; in rzg2l_cru_ip_s_stream() local
55 cru = v4l2_get_subdevdata(sd); in rzg2l_cru_ip_s_stream()
58 ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); in rzg2l_cru_ip_s_stream()
62 ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); in rzg2l_cru_ip_s_stream()
67 rzg2l_cru_stop_image_processing(cru); in rzg2l_cru_ip_s_stream()
69 ret = v4l2_subdev_call(cru->ip.remote, video, pre_streamon, 0); in rzg2l_cru_ip_s_stream()
[all …]
H A Drzg2l-cru.h3 * Driver for Renesas RZ/G2L CRU
61 * struct rzg2l_cru_dev - Renesas CRU device structure
64 * @info: info about CRU instance
69 * @vclk: CRU Main clock
73 * @vdev: V4L2 video device associated with CRU
136 int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru);
137 void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru);
139 int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru);
140 void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru);
142 int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru);
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
450 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
451 <&cru CLK_GPU_STACKS>;
466 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
467 <&cru ACLK_USB3OTG0>;
474 resets = <&cru SRST_A_USB3OTG0>;
488 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
499 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
510 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
[all …]
H A Drk3588-extra.dtsi14 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
15 <&cru ACLK_USB3OTG1>;
22 resets = <&cru SRST_A_USB3OTG1>;
55 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
59 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
74 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
77 assigned-clock-parents = <&cru PLL_AUPLL>;
81 resets = <&cru SRST_M_I2S8_8CH_TX>;
91 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
[all …]
H A Drk356x.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
298 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
299 <&cru CLK_SATA1_RXOOB>;
312 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
313 <&cru CLK_SATA2_RXOOB>;
327 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
328 <&cru ACLK_USB3OTG0>;
334 resets = <&cru SRST_USB3OTG0>;
343 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
344 <&cru ACLK_USB3OTG1>;
[all …]
H A Drk3399-base.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
85 clocks = <&cru ARMCLKL>;
104 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKL>;
142 clocks = <&cru ARMCLKL>;
161 clocks = <&cru ARMCLKB>;
186 clocks = <&cru ARMCLKB>;
255 clocks = <&cru SCLK_DDRC>;
302 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
303 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
[all …]
H A Drk3568.dtsi14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
15 <&cru CLK_SATA0_RXOOB>;
55 <&cru PCLK_PCIE30PHY>;
57 resets = <&cru SRST_PCIE30PHY>;
68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
70 <&cru CLK_PCIE30X1_AUX_NDFT>;
102 resets = <&cru SRST_PCIE30X1_POWERUP>;
121 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
122 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
[all …]
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
H A Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
191 resets = <&cru SRST_MMC0>;
200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
205 resets = <&cru SRST_SDIO0>;
214 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
219 resets = <&cru SRST_EMMC>;
[all …]
H A Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
269 clocks = <&cru HCLK_HOST>,
270 <&cru HCLK_OTG>,
271 <&cru SCLK_OTG_ADP>;
277 clocks = <&cru HCLK_SDMMC>,
278 <&cru SCLK_SDMMC>;
[all …]
H A Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
201 assigned-clocks = <&cru USB480M>;
203 clocks = <&cru SCLK_USBPHY_REF>;
245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
284 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
297 clocks = <&cru PCLK_WDT>;
306 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
43 clocks = <&cru ARMCLK>;
51 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
67 clocks = <&cru ARMCLK>;
186 clocks = <&cru HCLK_EMMC>,
187 <&cru CLK_EMMC>,
188 <&cru HCLK_NANDC>,
189 <&cru CLK_NANDC>,
190 <&cru HCLK_SFC>,
[all …]
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
40 clocks = <&cru ARMCLK>;
48 resets = <&cru SRST_CORE1>;
58 resets = <&cru SRST_CORE2>;
68 resets = <&cru SRST_CORE3>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
157 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
167 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
181 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
70 resets = <&cru SRST_CORE0>;
74 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE1>;
85 clocks = <&cru ARMCLK>;
92 resets = <&cru SRST_CORE2>;
96 clocks = <&cru ARMCLK>;
103 resets = <&cru SRST_CORE3>;
107 clocks = <&cru ARMCLK>;
208 clocks = <&cru PCLK_TIMER>, <&xin24m>;
[all …]
H A Drk3128.dtsi6 #include <dt-bindings/clock/rk3128-cru.h>
52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CORE0>;
62 resets = <&cru SRST_CORE1>;
70 resets = <&cru SRST_CORE2>;
78 resets = <&cru SRST_CORE3>;
190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
193 resets = <&cru SRST_GPU>;
210 clocks = <&cru ACLK_CIF>,
211 <&cru HCLK_CIF>,
[all …]
H A Drk3xxx.dtsi46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PERI>;
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 clocks = <&cru HCLK_OTG0>;
[all …]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
[all …]
H A Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
44 resets = <&cru SRST_CORE0>;
50 clocks = <&cru ARMCLK>;
57 resets = <&cru SRST_CORE1>;
114 assigned-clocks = <&cru SCLK_GPU>;
116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
119 resets = <&cru SRST_GPU>;
128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
138 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
148 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
[all …]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
199 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
[all …]
H A Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
27 clocks = <&cru ARMCLK>;
29 resets = <&cru SRST_CORE0>;
37 resets = <&cru SRST_CORE1>;
45 resets = <&cru SRST_CORE2>;
53 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
43 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44 <&cru SCLK_UPHY0_TCPDPHY_REF>;
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
48 resets = <&cru SRST_UPHY0>,
49 <&cru SRST_UPHY0_PIPE_L00>,
50 <&cru SRST_P_UPHY0_TCPHY>;
67 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68 <&cru SCLK_UPHY1_TCPDPHY_REF>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Drenesas,rzg2l-cru.yaml5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing
14 The CRU image processing module is a data conversion module equipped with pixel
22 - renesas,r9a07g043-cru # RZ/G2UL
23 - renesas,r9a07g044-cru # RZ/G2{L,LC}
24 - renesas,r9a07g054-cru # RZ/V2L
25 - const: renesas,rzg2l-cru
41 - description: CRU Main clock
42 - description: CRU Register access clock
43 - description: CRU image transfer clock
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml42 #include <dt-bindings/clock/rk3399-cru.h>
52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;

12345678910>>...12