Lines Matching full:cru
14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
15 <&cru CLK_SATA0_RXOOB>;
55 <&cru PCLK_PCIE30PHY>;
57 resets = <&cru SRST_PCIE30PHY>;
68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
70 <&cru CLK_PCIE30X1_AUX_NDFT>;
102 resets = <&cru SRST_PCIE30X1_POWERUP>;
121 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
122 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
123 <&cru CLK_PCIE30X2_AUX_NDFT>;
155 resets = <&cru SRST_PCIE30X2_POWERUP>;
175 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
176 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
177 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
178 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
183 resets = <&cru SRST_A_GMAC0>;
220 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
222 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
233 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
235 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
246 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
248 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
259 <&cru PCLK_PIPEPHY0>,
260 <&cru PCLK_PIPE>;
264 resets = <&cru SRST_PIPEPHY0>;
286 clocks = <&cru PCLK_PIPE>;