Lines Matching full:cru
14 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
15 <&cru ACLK_USB3OTG1>;
22 resets = <&cru SRST_A_USB3OTG1>;
55 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
59 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
74 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
77 assigned-clock-parents = <&cru PLL_AUPLL>;
81 resets = <&cru SRST_M_I2S8_8CH_TX>;
91 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
94 assigned-clock-parents = <&cru PLL_AUPLL>;
98 resets = <&cru SRST_M_I2S6_8CH_TX>;
108 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
111 assigned-clock-parents = <&cru PLL_AUPLL>;
115 resets = <&cru SRST_M_I2S7_8CH_RX>;
125 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
128 assigned-clock-parents = <&cru PLL_AUPLL>;
132 resets = <&cru SRST_M_I2S10_8CH_RX>;
143 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
144 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
145 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
176 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
197 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
198 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
199 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
219 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
229 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
230 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
231 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
262 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
278 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
279 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
280 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
311 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
332 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
333 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
334 <&cru CLK_GMAC0_PTP_REF>;
339 resets = <&cru SRST_A_GMAC0>;
379 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
380 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
381 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
402 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
403 <&cru CLK_USBDP_PHY1_IMMORTAL>,
404 <&cru PCLK_USBDPPHY1>,
407 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
408 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
409 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
410 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
411 <&cru SRST_P_USBDPPHY1>;
423 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
424 <&cru PCLK_PHP_ROOT>;
426 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
429 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
440 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
442 resets = <&cru SRST_PCIE30_PHY>;