Lines Matching full:cru
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
450 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
451 <&cru CLK_GPU_STACKS>;
466 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
467 <&cru ACLK_USB3OTG0>;
474 resets = <&cru SRST_A_USB3OTG0>;
488 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
499 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
510 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
521 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
532 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
533 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
534 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
540 resets = <&cru SRST_A_USB3OTG2>;
591 clocks = <&cru PCLK_VO0GRF>;
597 clocks = <&cru PCLK_VO1GRF>;
635 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
639 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
660 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
664 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
685 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
689 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
718 cru: clock-controller@fd7c0000 { label
719 compatible = "rockchip,rk3588-cru";
722 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
723 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
724 <&cru ACLK_CENTER_ROOT>,
725 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
726 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
727 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
728 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
729 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
730 <&cru CLK_GPU>;
750 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
763 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
777 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
788 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
799 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
810 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
838 clocks = <&cru HCLK_NPU_ROOT>,
839 <&cru PCLK_NPU_ROOT>,
840 <&cru CLK_NPU_DSU0>,
841 <&cru HCLK_NPU_CM0_ROOT>;
851 clocks = <&cru HCLK_NPU_ROOT>,
852 <&cru PCLK_NPU_ROOT>,
853 <&cru CLK_NPU_DSU0>;
859 clocks = <&cru HCLK_NPU_ROOT>,
860 <&cru PCLK_NPU_ROOT>,
861 <&cru CLK_NPU_DSU0>;
870 clocks = <&cru CLK_GPU>,
871 <&cru CLK_GPU_COREGROUP>,
872 <&cru CLK_GPU_STACKS>;
888 clocks = <&cru HCLK_RKVDEC0>,
889 <&cru HCLK_VDPU_ROOT>,
890 <&cru ACLK_VDPU_ROOT>,
891 <&cru ACLK_RKVDEC0>,
892 <&cru ACLK_RKVDEC_CCU>;
898 clocks = <&cru HCLK_RKVDEC1>,
899 <&cru HCLK_VDPU_ROOT>,
900 <&cru ACLK_VDPU_ROOT>,
901 <&cru ACLK_RKVDEC1>;
907 clocks = <&cru HCLK_RKVENC0>,
908 <&cru ACLK_RKVENC0>;
918 clocks = <&cru HCLK_RKVENC1>,
919 <&cru HCLK_RKVENC0>,
920 <&cru ACLK_RKVENC0>,
921 <&cru ACLK_RKVENC1>;
932 clocks = <&cru HCLK_VDPU_ROOT>,
933 <&cru ACLK_VDPU_LOW_ROOT>,
934 <&cru ACLK_VDPU_ROOT>,
935 <&cru ACLK_JPEG_DECODER_ROOT>,
936 <&cru ACLK_IEP2P0>,
937 <&cru HCLK_IEP2P0>,
938 <&cru ACLK_JPEG_ENCODER0>,
939 <&cru HCLK_JPEG_ENCODER0>,
940 <&cru ACLK_JPEG_ENCODER1>,
941 <&cru HCLK_JPEG_ENCODER1>,
942 <&cru ACLK_JPEG_ENCODER2>,
943 <&cru HCLK_JPEG_ENCODER2>,
944 <&cru ACLK_JPEG_ENCODER3>,
945 <&cru HCLK_JPEG_ENCODER3>,
946 <&cru ACLK_JPEG_DECODER>,
947 <&cru HCLK_JPEG_DECODER>,
948 <&cru ACLK_RGA2>,
949 <&cru HCLK_RGA2>;
965 clocks = <&cru PCLK_AV1>,
966 <&cru ACLK_AV1>,
967 <&cru HCLK_VDPU_ROOT>;
973 clocks = <&cru HCLK_RKVDEC0>,
974 <&cru HCLK_VDPU_ROOT>,
975 <&cru ACLK_VDPU_ROOT>,
976 <&cru ACLK_RKVDEC0>;
982 clocks = <&cru HCLK_RKVDEC1>,
983 <&cru HCLK_VDPU_ROOT>,
984 <&cru ACLK_VDPU_ROOT>;
990 clocks = <&cru ACLK_RGA3_0>,
991 <&cru HCLK_RGA3_0>;
998 clocks = <&cru PCLK_VOP_ROOT>,
999 <&cru HCLK_VOP_ROOT>,
1000 <&cru ACLK_VOP>;
1009 clocks = <&cru PCLK_VO0_ROOT>,
1010 <&cru PCLK_VO0_S_ROOT>,
1011 <&cru HCLK_VO0_S_ROOT>,
1012 <&cru ACLK_VO0_ROOT>,
1013 <&cru HCLK_HDCP0>,
1014 <&cru ACLK_HDCP0>,
1015 <&cru HCLK_VOP_ROOT>;
1022 clocks = <&cru PCLK_VO1_ROOT>,
1023 <&cru PCLK_VO1_S_ROOT>,
1024 <&cru HCLK_VO1_S_ROOT>,
1025 <&cru HCLK_HDCP1>,
1026 <&cru ACLK_HDCP1>,
1027 <&cru ACLK_HDMIRX_ROOT>,
1028 <&cru HCLK_VO1USB_TOP_ROOT>;
1035 clocks = <&cru HCLK_VI_ROOT>,
1036 <&cru PCLK_VI_ROOT>,
1037 <&cru HCLK_ISP0>,
1038 <&cru ACLK_ISP0>,
1039 <&cru HCLK_VICAP>,
1040 <&cru ACLK_VICAP>;
1051 clocks = <&cru HCLK_ISP1>,
1052 <&cru ACLK_ISP1>,
1053 <&cru HCLK_VI_ROOT>,
1054 <&cru PCLK_VI_ROOT>;
1061 clocks = <&cru HCLK_FISHEYE0>,
1062 <&cru ACLK_FISHEYE0>,
1063 <&cru HCLK_FISHEYE1>,
1064 <&cru ACLK_FISHEYE1>,
1065 <&cru PCLK_VI_ROOT>;
1073 clocks = <&cru HCLK_RGA3_1>,
1074 <&cru ACLK_RGA3_1>;
1080 clocks = <&cru PCLK_PHP_ROOT>,
1081 <&cru ACLK_USB_ROOT>,
1082 <&cru ACLK_USB>,
1083 <&cru HCLK_USB_ROOT>,
1084 <&cru HCLK_HOST0>,
1085 <&cru HCLK_HOST_ARB0>,
1086 <&cru HCLK_HOST1>,
1087 <&cru HCLK_HOST_ARB1>;
1096 clocks = <&cru PCLK_PHP_ROOT>,
1097 <&cru ACLK_PCIE_ROOT>,
1098 <&cru ACLK_PHP_ROOT>;
1103 clocks = <&cru PCLK_PHP_ROOT>,
1104 <&cru ACLK_PCIE_ROOT>,
1105 <&cru ACLK_PHP_ROOT>;
1110 clocks = <&cru HCLK_SDIO>,
1111 <&cru HCLK_NVM_ROOT>;
1117 clocks = <&cru HCLK_AUDIO_ROOT>,
1118 <&cru PCLK_AUDIO_ROOT>;
1134 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1145 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1154 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
1156 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>;
1165 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1175 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1185 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1195 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1205 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1215 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1225 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1235 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1246 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1248 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1251 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
1259 clocks = <&cru ACLK_VOP>,
1260 <&cru HCLK_VOP>,
1261 <&cru DCLK_VOP0>,
1262 <&cru DCLK_VOP1>,
1263 <&cru DCLK_VOP2>,
1264 <&cru DCLK_VOP3>,
1265 <&cru PCLK_VOP_ROOT>;
1315 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1326 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1328 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1329 assigned-clock-parents = <&cru PLL_AUPLL>;
1333 resets = <&cru SRST_M_I2S4_8CH_TX>;
1343 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1345 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1346 assigned-clock-parents = <&cru PLL_AUPLL>;
1350 resets = <&cru SRST_M_I2S5_8CH_TX>;
1360 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1362 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1363 assigned-clock-parents = <&cru PLL_AUPLL>;
1367 resets = <&cru SRST_M_I2S9_8CH_RX>;
1626 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1627 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1628 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1659 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1677 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1678 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1679 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1710 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1731 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1732 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1733 <&cru CLK_GMAC1_PTP_REF>;
1738 resets = <&cru SRST_A_GMAC1>;
1778 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1779 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1780 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1801 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1802 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1803 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1824 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1836 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1850 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1851 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1865 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1867 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1868 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1869 <&cru TMCLK_EMMC>;
1875 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1876 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1877 <&cru SRST_T_EMMC>;
1886 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1888 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1889 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1893 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1915 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1919 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1941 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1943 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1944 assigned-clock-parents = <&cru PLL_AUPLL>;
1961 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1963 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1964 assigned-clock-parents = <&cru PLL_AUPLL>;
2022 clocks = <&cru ACLK_DMAC0>;
2033 clocks = <&cru ACLK_DMAC1>;
2041 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2054 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2067 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2080 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2093 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2107 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
2114 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
2123 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
2139 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
2155 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
2171 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
2187 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
2202 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
2217 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
2232 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
2247 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2262 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2277 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2292 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2307 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2321 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2332 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2343 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2354 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2365 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2376 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2387 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2398 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2409 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2420 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2431 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2442 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2620 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2622 assigned-clocks = <&cru CLK_TSADC>;
2624 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2627 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2641 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2643 resets = <&cru SRST_P_SARADC>;
2651 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2664 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2677 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2691 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2706 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2707 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2709 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2710 <&cru SRST_OTPC_ARB>;
2763 clocks = <&cru ACLK_DMAC2>;
2771 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2774 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2775 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2776 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2777 <&cru SRST_HDPTX0_LCPLL>;
2788 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
2789 <&cru CLK_USBDP_PHY0_IMMORTAL>,
2790 <&cru PCLK_USBDPPHY0>,
2793 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
2794 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
2795 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
2796 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
2797 <&cru SRST_P_USBDPPHY0>;
2809 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2810 <&cru PCLK_PHP_ROOT>;
2812 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2815 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2825 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2826 <&cru PCLK_PHP_ROOT>;
2828 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2831 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2857 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2869 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2881 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2893 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2905 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;