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/linux/drivers/amba/
H A Dtegra-ahb.c21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
146 ahb = dev_get_drvdata(dev); in tegra_ahb_enable_smmu()
147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
[all …]
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-ahb.yaml4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
11 title: NVIDIA Tegra AHB
17 - nvidia,tegra20-ahb
18 - nvidia,tegra30-ahb
21 - nvidia,tegra114-ahb
22 - nvidia,tegra124-ahb
23 - nvidia,tegra210-ahb
24 - const: nvidia,tegra30-ahb
37 ahb@6000c004 {
38 compatible = "nvidia,tegra20-ahb";
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx35.c33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
44 { .arm = 1, .ahb = 5, .sel = 0},
45 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
H A Dclk-imx27.c40 "ahb", "ipg", "per1_div", "per2_div",
69 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
72 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
73 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
76 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
77 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
139 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
140 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
141 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
H A Dclk-imx25.c47 static const char *per_sel_clks[] = { "ahb", "upll", };
48 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
145 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
146 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
H A Dclk-imx31.c39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
64 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
82 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
100 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
111 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
112 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
H A Dclk-imx6ul.c65 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
306 hws[IMX6UL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); in imx6ul_clocks_init()
345 …hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0… in imx6ul_clocks_init()
348 …hws[IMX6UL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICA… in imx6ul_clocks_init()
349 …hws[IMX6UL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICA… in imx6ul_clocks_init()
351 …hws[IMX6UL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count… in imx6ul_clocks_init()
352 …hws[IMX6UL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count… in imx6ul_clocks_init()
354 hws[IMX6UL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); in imx6ul_clocks_init()
355 hws[IMX6UL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); in imx6ul_clocks_init()
358 hws[IMX6ULL_CLK_DCP_CLK] = imx_clk_hw_gate2("dcp", "ahb", base + 0x68, 10); in imx6ul_clocks_init()
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c246 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
267 .hw.init = CLK_HW_INIT_PARENTS("ahb",
281 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
292 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
295 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
297 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
299 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
301 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
303 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
305 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
H A Dccu-sun5i.c214 .hw.init = CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
H A Dccu-suniv-f1c100s.c132 .hw.init = CLK_HW_INIT_PARENTS("ahb",
146 static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
149 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
151 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
153 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
155 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
157 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
159 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
161 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
164 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
[all …]
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c281 * peripheral clocks - devices connected to axi or ahb buses.
300 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
301 * if the AHB interface clock is disabled
309 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
310 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
311 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
312 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
314 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
315 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
316 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
[all …]
/linux/drivers/clk/
H A Dclk-gemini.c91 { 2, "gmac0-gate", "ahb", 0 },
92 { 3, "gmac1-gate", "ahb", 0 },
93 { 4, "sata0-gate", "ahb", 0 },
94 { 5, "sata1-gate", "ahb", 0 },
95 { 6, "usb0-gate", "ahb", 0 },
96 { 7, "usb1-gate", "ahb", 0 },
97 { 8, "ide-gate", "ahb", 0 },
98 { 9, "pci-gate", "ahb", 0 },
103 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
108 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
H A Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
H A Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
H A Dallwinner,sun9i-a80-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
H A Dallwinner,sun4i-a10-gates-clk.yaml26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
H A Dstarfive,jh7110-aoncrg.yaml24 - description: STG AXI/AHB
31 - description: STG AXI/AHB or GMAC0 RGMII RX
32 - description: APB Bus or STG AXI/AHB
40 - description: STG AXI/AHB
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c524 static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
1339 static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
1385 static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
1387 static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
1389 static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
1391 static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
1393 static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
1395 static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
1397 static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
1399 static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml95 - const: s-ahb
99 - description: Slave AHB Clock
110 - const: m-ahb
111 - const: s-ahb
115 - description: Master AHB Clock
116 - description: Slave AHB Clock
132 clock-names = "m-ahb", "s-ahb";
/linux/drivers/dma/dw/
H A DKconfig12 tristate "Synopsys DesignWare AHB DMA platform driver"
16 Support the Synopsys DesignWare AHB DMA controller. This
25 the Synopsys DesignWare AHB DMA controller located on Renesas
29 tristate "Synopsys DesignWare AHB DMA PCI driver"
34 Support the Synopsys DesignWare AHB DMA controller on the
/linux/Documentation/devicetree/bindings/misc/
H A Dintel,ixp4xx-ahb-queue-manager.yaml5 $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
/linux/drivers/char/hw_random/
H A Djh7110-trng.c99 struct clk *ahb; member
242 clk_disable_unprepare(trng->ahb); in starfive_trng_cleanup()
311 trng->ahb = devm_clk_get(&pdev->dev, "ahb"); in starfive_trng_probe()
312 if (IS_ERR(trng->ahb)) in starfive_trng_probe()
313 return dev_err_probe(&pdev->dev, PTR_ERR(trng->ahb), in starfive_trng_probe()
314 "Error getting ahb reference clock\n"); in starfive_trng_probe()
322 clk_prepare_enable(trng->ahb); in starfive_trng_probe()
343 clk_disable_unprepare(trng->ahb); in starfive_trng_probe()
357 clk_disable_unprepare(trng->ahb); in starfive_trng_suspend()
367 clk_prepare_enable(trng->ahb); in starfive_trng_resume()
/linux/Documentation/devicetree/bindings/iommu/
H A Dnvidia,tegra30-smmu.txt10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
/linux/Documentation/devicetree/bindings/mtd/
H A Dallwinner,sun4i-a10-nand.yaml34 - const: ahb
41 const: ahb
100 clock-names = "ahb", "mod";
102 reset-names = "ahb";

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