21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79  * 0x4 for the AHB IP block.  According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)  in gizmo_readl()  argument
128 	return readl(ahb->regs + offset);  in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)  in gizmo_writel()  argument
133 	writel(value, ahb->regs + offset);  in gizmo_writel()
141 	struct tegra_ahb *ahb;  in tegra_ahb_enable_smmu()  local
146 	ahb = dev_get_drvdata(dev);  in tegra_ahb_enable_smmu()
147 	val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);  in tegra_ahb_enable_smmu()
149 	gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);  in tegra_ahb_enable_smmu()
158 	struct tegra_ahb *ahb = dev_get_drvdata(dev);  in tegra_ahb_suspend()  local
161 		ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);  in tegra_ahb_suspend()
168 	struct tegra_ahb *ahb = dev_get_drvdata(dev);  in tegra_ahb_resume()  local
171 		gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);  in tegra_ahb_resume()
179 static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)  in tegra_ahb_gizmo_init()  argument
183 	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);  in tegra_ahb_gizmo_init()
185 	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);  in tegra_ahb_gizmo_init()
187 	val = gizmo_readl(ahb, AHB_GIZMO_USB);  in tegra_ahb_gizmo_init()
189 	gizmo_writel(ahb, val, AHB_GIZMO_USB);  in tegra_ahb_gizmo_init()
191 	val = gizmo_readl(ahb, AHB_GIZMO_USB2);  in tegra_ahb_gizmo_init()
193 	gizmo_writel(ahb, val, AHB_GIZMO_USB2);  in tegra_ahb_gizmo_init()
195 	val = gizmo_readl(ahb, AHB_GIZMO_USB3);  in tegra_ahb_gizmo_init()
197 	gizmo_writel(ahb, val, AHB_GIZMO_USB3);  in tegra_ahb_gizmo_init()
199 	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);  in tegra_ahb_gizmo_init()
204 	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);  in tegra_ahb_gizmo_init()
206 	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);  in tegra_ahb_gizmo_init()
212 	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);  in tegra_ahb_gizmo_init()
214 	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);  in tegra_ahb_gizmo_init()
220 	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);  in tegra_ahb_gizmo_init()
222 	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);  in tegra_ahb_gizmo_init()
228 	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);  in tegra_ahb_gizmo_init()
230 	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);  in tegra_ahb_gizmo_init()
236 	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);  in tegra_ahb_gizmo_init()
242 	struct tegra_ahb *ahb;  in tegra_ahb_probe()  local
245 	bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);  in tegra_ahb_probe()
246 	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);  in tegra_ahb_probe()
247 	if (!ahb)  in tegra_ahb_probe()
256 		dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");  in tegra_ahb_probe()
260 	ahb->regs = devm_ioremap_resource(&pdev->dev, res);  in tegra_ahb_probe()
261 	if (IS_ERR(ahb->regs))  in tegra_ahb_probe()
262 		return PTR_ERR(ahb->regs);  in tegra_ahb_probe()
264 	ahb->dev = &pdev->dev;  in tegra_ahb_probe()
265 	platform_set_drvdata(pdev, ahb);  in tegra_ahb_probe()
266 	tegra_ahb_gizmo_init(ahb);  in tegra_ahb_probe()
271 	{ .compatible = "nvidia,tegra30-ahb", },
272 	{ .compatible = "nvidia,tegra20-ahb", },
287 MODULE_DESCRIPTION("Tegra AHB driver");