Lines Matching full:ahb

246 		.hw.init	= CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
267 		.hw.init	= CLK_HW_INIT_PARENTS("ahb",
281 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
292 static SUNXI_CCU_GATE(axi_dram_clk,	"axi-dram",	"ahb",
295 static SUNXI_CCU_GATE(ahb_otg_clk,	"ahb-otg",	"ahb",
297 static SUNXI_CCU_GATE(ahb_ehci0_clk,	"ahb-ehci0",	"ahb",
299 static SUNXI_CCU_GATE(ahb_ohci0_clk,	"ahb-ohci0",	"ahb",
301 static SUNXI_CCU_GATE(ahb_ehci1_clk,	"ahb-ehci1",	"ahb",
303 static SUNXI_CCU_GATE(ahb_ohci1_clk,	"ahb-ohci1",	"ahb",
305 static SUNXI_CCU_GATE(ahb_ss_clk,	"ahb-ss",	"ahb",
307 static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",
309 static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",
311 static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",
313 static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",
315 static SUNXI_CCU_GATE(ahb_mmc2_clk,	"ahb-mmc2",	"ahb",
317 static SUNXI_CCU_GATE(ahb_mmc3_clk,	"ahb-mmc3",	"ahb",
319 static SUNXI_CCU_GATE(ahb_ms_clk,	"ahb-ms",	"ahb",
321 static SUNXI_CCU_GATE(ahb_nand_clk,	"ahb-nand",	"ahb",
323 static SUNXI_CCU_GATE(ahb_sdram_clk,	"ahb-sdram",	"ahb",
326 static SUNXI_CCU_GATE(ahb_ace_clk,	"ahb-ace",	"ahb",
328 static SUNXI_CCU_GATE(ahb_emac_clk,	"ahb-emac",	"ahb",
330 static SUNXI_CCU_GATE(ahb_ts_clk,	"ahb-ts",	"ahb",
332 static SUNXI_CCU_GATE(ahb_spi0_clk,	"ahb-spi0",	"ahb",
334 static SUNXI_CCU_GATE(ahb_spi1_clk,	"ahb-spi1",	"ahb",
336 static SUNXI_CCU_GATE(ahb_spi2_clk,	"ahb-spi2",	"ahb",
338 static SUNXI_CCU_GATE(ahb_spi3_clk,	"ahb-spi3",	"ahb",
340 static SUNXI_CCU_GATE(ahb_pata_clk,	"ahb-pata",	"ahb",
343 static SUNXI_CCU_GATE(ahb_sata_clk,	"ahb-sata",	"ahb",
346 static SUNXI_CCU_GATE(ahb_gps_clk,	"ahb-gps",	"ahb",
349 static SUNXI_CCU_GATE(ahb_hstimer_clk,	"ahb-hstimer",	"ahb",
352 static SUNXI_CCU_GATE(ahb_ve_clk,	"ahb-ve",	"ahb",
354 static SUNXI_CCU_GATE(ahb_tvd_clk,	"ahb-tvd",	"ahb",
356 static SUNXI_CCU_GATE(ahb_tve0_clk,	"ahb-tve0",	"ahb",
358 static SUNXI_CCU_GATE(ahb_tve1_clk,	"ahb-tve1",	"ahb",
360 static SUNXI_CCU_GATE(ahb_lcd0_clk,	"ahb-lcd0",	"ahb",
362 static SUNXI_CCU_GATE(ahb_lcd1_clk,	"ahb-lcd1",	"ahb",
364 static SUNXI_CCU_GATE(ahb_csi0_clk,	"ahb-csi0",	"ahb",
366 static SUNXI_CCU_GATE(ahb_csi1_clk,	"ahb-csi1",	"ahb",
369 static SUNXI_CCU_GATE(ahb_hdmi1_clk,	"ahb-hdmi1",	"ahb",
371 static SUNXI_CCU_GATE(ahb_hdmi0_clk,	"ahb-hdmi0",	"ahb",
373 static SUNXI_CCU_GATE(ahb_de_be0_clk,	"ahb-de-be0",	"ahb",
375 static SUNXI_CCU_GATE(ahb_de_be1_clk,	"ahb-de-be1",	"ahb",
377 static SUNXI_CCU_GATE(ahb_de_fe0_clk,	"ahb-de-fe0",	"ahb",
379 static SUNXI_CCU_GATE(ahb_de_fe1_clk,	"ahb-de-fe1",	"ahb",
382 static SUNXI_CCU_GATE(ahb_gmac_clk,	"ahb-gmac",	"ahb",
384 static SUNXI_CCU_GATE(ahb_mp_clk,	"ahb-mp",	"ahb",
386 static SUNXI_CCU_GATE(ahb_gpu_clk,	"ahb-gpu",	"ahb",
1458 	 * Use the peripheral PLL6 as the AHB parent, instead of CPU /  in sun4i_a10_ccu_probe()
1462 	 * clock is AHB.  in sun4i_a10_ccu_probe()