33 	unsigned char arm, ahb, sel;  member
37 	{ .arm = 1, .ahb = 4, .sel = 0},
38 	{ .arm = 1, .ahb = 3, .sel = 1},
39 	{ .arm = 2, .ahb = 2, .sel = 0},
40 	{ .arm = 0, .ahb = 0, .sel = 0},
41 	{ .arm = 0, .ahb = 0, .sel = 0},
42 	{ .arm = 0, .ahb = 0, .sel = 0},
43 	{ .arm = 4, .ahb = 1, .sel = 0},
44 	{ .arm = 1, .ahb = 5, .sel = 0},
45 	{ .arm = 1, .ahb = 8, .sel = 0},
46 	{ .arm = 1, .ahb = 6, .sel = 1},
47 	{ .arm = 2, .ahb = 4, .sel = 0},
48 	{ .arm = 0, .ahb = 0, .sel = 0},
49 	{ .arm = 0, .ahb = 0, .sel = 0},
50 	{ .arm = 0, .ahb = 0, .sel = 0},
51 	{ .arm = 4, .ahb = 2, .sel = 0},
52 	{ .arm = 0, .ahb = 0, .sel = 0},
64 	/*  0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,  enumerator
131 	clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);  in _mx35_clocks_init()
132 	clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);  in _mx35_clocks_init()
135 	clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);  in _mx35_clocks_init()
159 	clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);  in _mx35_clocks_init()
192 	clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);  in _mx35_clocks_init()
199 	clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2,  2);  in _mx35_clocks_init()
201 	clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2,  6);  in _mx35_clocks_init()
209 	clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);  in _mx35_clocks_init()
216 	clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);  in _mx35_clocks_init()