| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]
|
| H A D | renesas,rza2-pinctrl.txt | 1 Renesas RZ/A2 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
5 Each port features up to 8 pins, each of them configurable for GPIO
7 Up to 8 different alternate function modes exist for each single pin.
9 Pin controller node
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
[all …]
|
| H A D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
|
| H A D | sunplus,sp7021-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | sama5d3_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
|
| H A D | at91sam9x5_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
|
| /freebsd/sys/arm64/rockchip/ |
| H A D | rk_pinctrl.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
75 uint32_t pin; member
114 #define RK_PINCTRL_LOCK(_sc) mtx_lock_spin(&(_sc)->mtx)
115 #define RK_PINCTRL_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->mtx)
116 #define RK_PINCTRL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
129 .pin = _pin, \
158 RK_GPIO(8, "gpio8"),
181 /* 5,0 - Empty */
184 /* 5,3 - Empty */
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos3250-artik5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = &serial_2;
35 compatible = "samsung,secure-firmware";
39 thermal-zones {
40 cpu_thermal: cpu-thermal {
41 cooling-maps {
44 cooling-device = <&cpu0 5 5>,
[all …]
|
| H A D | s3c64xx-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
[all …]
|
| H A D | exynos4210-i9100.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-even
[all...] |
| H A D | s5pv210-aries.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
[all …]
|
| H A D | exynos5250-spring.dts | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
19 chassis-type = "laptop";
33 stdout-path = "serial3:115200n8";
36 gpio-keys {
37 compatible = "gpio-keys";
[all …]
|
| H A D | exynos5250-snow-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm64/actions/ |
| H A D | s900-bubblegum-96.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
[all …]
|
| /freebsd/usr.sbin/bluetooth/hcsecd/ |
| H A D | hcsecd.conf.5 | 1 .\" Copyright (c) 2001-2002 Maksim Yevmenkin <m_evmenkin@yahoo.com>
33 .Xr hcsecd 8
39 .Xr hcsecd 8
40 Bluetooth link keys/PIN codes management daemon.
44 file is a free-form
47 It is parsed by the recursive-descent parser built into
48 .Xr hcsecd 8 .
50 Keywords in the file are case-sensitive.
63 entry defines a link key or PIN code for a remote Bluetooth device.
79 .Bl -tag -width indent
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/ |
| H A D | pincfg.txt | 1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
[all …]
|
| H A D | mdio-mux-gpio.txt | 8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
30 mdio-parent-bus = <&smi1>;
31 #address-cells = <1>;
[all …]
|
| H A D | mdio-mux.txt | 8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
26 compatible = "cavium,octeon-3860-mdio";
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | snd_hda.4 | 2 .\" SPDX-License-Identifier: BSD-2-Clause
4 .\" Copyright (c) 2006-2008 Joel Dahl <joel@FreeBSD.org>
38 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
84 .Xr sysctl 8 .
93 .Ss Boot-time Configuration
94 The following variables are available at boot-time through the
97 .Bl -tag -width ".Va hint.hdac.%d.config"-offset indent
158 Zero out the pin widget config setup by the system.
159 Some systems seem to have unusable audio devices if the pin widget
[all …]
|
| /freebsd/share/man/man4/man4.arm/ |
| H A D | am335x_dmtpps.4 | 37 .Cd hw.am335x_dmtpps.input="pin name"
57 .Xr ntpd 8 ,
75 The driver uses system pin configuration to determine which hardware
77 Configure the timer input pin in the system's FDT data, or by
78 supplying the pin name using a tunable variable in
87 tunable variable to the name of the input pin, one of the following:
89 .Bl -tag -width "GPMC_ADVn_ALE MMMM" -offset MMMM -compact
92 .It P8-7
93 DMTimer4; Beaglebone P8 header pin 7.
94 .It P8-8
[all …]
|
| /freebsd/contrib/wpa/wpa_supplicant/examples/p2p/ |
| H A D | p2p_connect.py | 17 print(" %s -i <interface_name> -m <wps_method> \ " \
19 print(" -a <addr> [-p <pin>] [-g <go_intent>] \ ")
20 print(" [-w <wpas_dbus_interface>]")
22 print(" -i = interface name")
23 print(" -m = wps method")
24 print(" -a = peer address")
25 print(" -p = pin number (8 digits)")
26 print(" -g = group owner intent")
27 print(" -w = wpas dbus interface = fi.w1.wpa_supplicant1")
29 print(" %s -i wlan0 -a 0015008352c0 -m display -p 12345670" % sys.argv[0])
[all …]
|
| /freebsd/contrib/libfido2/man/ |
| H A D | fido2-token.1 | 1 .\" Copyright (c) 2018-2022 Yubico AB. All rights reserved.
26 .\" SPDX-License-Identifier: BSD-2-Clause
32 .Nm fido2-token
150 .Bl -tag -width Ds
152 Changes the PIN of
162 is the credential's base64-encoded id.
163 The user will be prompted for the PIN.
173 holds the blob's base64-encoded 32-byte AES-256 GCM encryption key.
174 A PIN or equivalent user-verification gesture is required.
190 is a base64-encoded blob.
[all …]
|
| /freebsd/sys/dev/nctgpio/ |
| H A D | nctgpio.c | 1 /*-
51 #define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */
63 #define NCT_PIN_IS_VALID(_sc, _p) ((_p) < (_sc)->npins)
64 #define NCT_PIN_GROUP(_sc, _p) ((_sc)->pinmap[(_p)].group)
65 #define NCT_PIN_GRPNUM(_sc, _p) ((_sc)->pinmap[(_p)].grpnum)
66 #define NCT_PIN_BIT(_sc, _p) ((_sc)->pinmap[(_p)].bit)
98 uint8_t ppod_reg; /* Push-Pull/Open-Drain */
100 uint8_t pinbits[8];
130 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
132 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
[all …]
|
| /freebsd/sys/dts/ |
| H A D | bindings-mpp.txt | 2 * Multi purpose pin (MPP) configuration.
6 - pin-map : array of pin configurations. Each pin is defined by 2 cells,
7 respectively: <pin> <function>. Pins not specified in the pin-map property
10 - pin : pin number.
12 - function : function ID of the pin according to the assignment tables in
13 User Manual. Each pin can have many possible functions depending on the
16 - pin-count: number of the physical MPP connections on the SOC (depending on
17 the model it can be 24-50, or possibly else in future devices).
22 #pin-cells = <2>;
25 pin-count= <50>;
[all …]
|