Home
last modified time | relevance | path

Searched +full:7 +full:- +full:bit (Results 1 – 25 of 1072) sorted by relevance

12345678910>>...43

/linux/include/linux/mfd/da9062/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
159 #define DA9062AA_REVERT_SHIFT 7
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
[all …]
/linux/include/linux/mfd/da9150/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
161 #define DA9150_REVERT_SHIFT 7
162 #define DA9150_REVERT_MASK BIT(7)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
181 #define DA9150_LFOSC_STAT_SHIFT 7
[all …]
/linux/drivers/platform/mellanox/
H A Dmlx-platform.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
17 #include <linux/platform_data/i2c-mux-reg.h>
229 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
230 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
231 #define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4)
232 #define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5)
240 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
[all …]
/linux/drivers/net/dsa/microchip/
H A Dlan937x_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
23 #define OVER_TEMP_INT BIT(28)
[all …]
H A Dksz8_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
28 #define KSZ8863_PCS_RESET BIT(0)
31 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)
35 #define SW_NEW_BACKOFF BIT(7)
36 #define SW_GLOBAL_RESET BIT(6)
37 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
38 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
39 #define SW_LINK_AUTO_AGING BIT(0)
43 #define SW_HUGE_PACKET BIT(6)
[all …]
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define SW_GIGABIT_ABLE BIT(6)
44 #define SW_REDUNDANCY_ABLE BIT(5)
45 #define SW_AVB_ABLE BIT(4)
63 #define SW_QW_ABLE BIT(5)
69 #define LUE_INT BIT(31)
70 #define TRIG_TS_INT BIT(30)
71 #define APB_TIMEOUT_INT BIT(29)
[all …]
/linux/include/linux/mfd/
H A Dtps6594.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
249 #define TPS6594_BIT_BUCK_EN BIT(0)
250 #define TPS6594_BIT_BUCK_FPWM BIT(1)
251 #define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
252 #define TPS6594_BIT_BUCK_VSEL BIT(3)
253 #define TPS6594_BIT_BUCK_VMON_EN BIT(4)
254 #define TPS6594_BIT_BUCK_PLDN BIT(5)
255 #define TPS6594_BIT_BUCK_RV_SEL BIT(7)
272 #define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
[all …]
H A Dtps65218.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
63 #define TPS65218_INT1_VPRG BIT(5)
64 #define TPS65218_INT1_AC BIT(4)
65 #define TPS65218_INT1_PB BIT(3)
66 #define TPS65218_INT1_HOT BIT(2)
67 #define TPS65218_INT1_CC_AQC BIT(1)
68 #define TPS65218_INT1_PRGC BIT(0)
70 #define TPS65218_INT2_LS3_F BIT(5)
71 #define TPS65218_INT2_LS2_F BIT(4)
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
[all …]
/linux/sound/soc/codecs/
H A Dwcd939x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
15 #define WCD939X_BIAS_ANALOG_BIAS_EN BIT(7)
16 #define WCD939X_BIAS_PRECHRG_EN BIT(6)
17 #define WCD939X_BIAS_PRECHRG_CTL_MODE BIT(5)
19 #define WCD939X_RX_SUPPLIES_VPOS_EN BIT(
[all...]
H A Dmt6357.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
[all …]
/linux/sound/soc/hisilicon/
H A Dhi6210-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
47 #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13)
[all …]
/linux/drivers/ufs/host/
H A Dufs-renesas.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
10 #include <linux/dma-mapping.h>
16 #include <linux/nvmem-consumer.h>
23 #include "ufshcd-pltfrm.h"
47 ret = readl_poll_timeout_atomic(hba->mmio_base + reg, in ufs_renesas_poll()
51 dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n", in ufs_renesas_poll()
75 ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr); in ufs_renesas_write_800_80c_poll()
77 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); in ufs_renesas_write_800_80c_poll()
83 ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr); in ufs_renesas_write_804_80c_poll()
85 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); in ufs_renesas_write_804_80c_poll()
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
197 BUS_MSTOP(5, BIT(9))),
199 BUS_MSTOP(3, BIT(2))),
201 BUS_MSTOP(3, BIT(3))),
203 BUS_MSTOP(10, BIT(11))),
205 BUS_MSTOP(10, BIT(12))),
209 BUS_MSTOP(3, BIT(5))),
[all …]
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
182 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
[all …]
/linux/drivers/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
24 PKT_TYPE_RX_EVENT = 7,
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define LR_SWAP BIT(0)
13 #define LFE_CC_SWAP BIT(1)
14 #define LSRS_SWAP BIT(2)
15 #define RLS_RRS_SWAP BIT(3)
16 #define LR_STATUS_SWAP BIT(4)
23 #define I2S_UV_V BIT(0)
24 #define I2S_UV_U BIT(1)
26 #define I2S_UV_CH_EN(x) BIT((x) + 2)
27 #define I2S_UV_TMDS_DEBUG BIT(6)
[all …]
/linux/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
128 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
129 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
130 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
132 #define DETECT_5V_A BIT(0) /* 5V present on input A */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Loading OCM re-trying times */
50 #define INTR_SOFTWARE_INT BIT(3)
51 #define INTR_RECEIVED_MSG BIT(5)
63 #define STORE_AN BIT(7)
64 #define RX_REPEATER BIT(6)
65 #define RE_AUTHEN BIT(5)
66 #define SW_AUTH_OK BIT(4)
67 #define HARD_AUTH_EN BIT(3)
68 #define ENC_EN BIT(2)
[all …]
/linux/drivers/power/supply/
H A Dqcom_smbx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
7 * This driver is for the switch-mode battery charger and boost
12 #include <linux/devm-helpers.h>
26 /* clang-format off */
28 #define BVR_INITIAL_RAMP_BIT BIT(7)
29 #define CC_SOFT_TERMINATE_BIT BIT(6)
35 #define INPUT_CURRENT_LIMITED_BIT BIT(7)
36 #define CHARGER_ERROR_STATUS_SFT_EXPIRE_BIT BIT(6)
37 #define CHARGER_ERROR_STATUS_BAT_OV_BIT BIT(5)
[all …]
/linux/drivers/net/ieee802154/
H A Dmcr20a.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
[all …]
/linux/include/soc/mscc/
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/linux/drivers/iio/dac/
H A Dad3552r.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AD3552R Digital <-> Analog converters common header
5 * Copyright 2021-2024 Analog Devices Inc.
15 #define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
17 #define AD3552R_MASK_SDO_ACTIVE BIT(4)
19 #define AD3552R_MASK_SINGLE_INST BIT(7)
20 #define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
22 #define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
26 #define AD3552R_MASK_CLASS GENMASK(7, 0)
[all …]
/linux/drivers/iio/frequency/
H A Dadf4377.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #define ADF4377_0000_SOFT_RESET_R_MSK BIT(7)
27 #define ADF4377_0000_LSB_FIRST_R_MSK BIT(6)
28 #define ADF4377_0000_ADDRESS_ASC_R_MSK BIT(5)
29 #define ADF4377_0000_SDO_ACTIVE_R_MSK BIT(4)
30 #define ADF4377_0000_SDO_ACTIVE_MSK BIT(3)
31 #define ADF4377_0000_ADDRESS_ASC_MSK BIT(2)
32 #define ADF4377_0000_LSB_FIRST_MSK BIT(1)
33 #define ADF4377_0000_SOFT_RESET_MSK BIT(0)
35 /* ADF4377 REG0000 Bit Definition */
[all …]

12345678910>>...43