1*1802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 28f83f268SJie Qiu /* 38f83f268SJie Qiu * Copyright (c) 2014 MediaTek Inc. 48f83f268SJie Qiu * Author: Jie Qiu <jie.qiu@mediatek.com> 58f83f268SJie Qiu */ 68f83f268SJie Qiu #ifndef _MTK_HDMI_REGS_H 78f83f268SJie Qiu #define _MTK_HDMI_REGS_H 88f83f268SJie Qiu 98f83f268SJie Qiu #define GRL_INT_MASK 0x18 108f83f268SJie Qiu #define GRL_IFM_PORT 0x188 118f83f268SJie Qiu #define GRL_CH_SWAP 0x198 128f83f268SJie Qiu #define LR_SWAP BIT(0) 138f83f268SJie Qiu #define LFE_CC_SWAP BIT(1) 148f83f268SJie Qiu #define LSRS_SWAP BIT(2) 158f83f268SJie Qiu #define RLS_RRS_SWAP BIT(3) 168f83f268SJie Qiu #define LR_STATUS_SWAP BIT(4) 178f83f268SJie Qiu #define GRL_I2S_C_STA0 0x140 188f83f268SJie Qiu #define GRL_I2S_C_STA1 0x144 198f83f268SJie Qiu #define GRL_I2S_C_STA2 0x148 208f83f268SJie Qiu #define GRL_I2S_C_STA3 0x14C 218f83f268SJie Qiu #define GRL_I2S_C_STA4 0x150 228f83f268SJie Qiu #define GRL_I2S_UV 0x154 238f83f268SJie Qiu #define I2S_UV_V BIT(0) 248f83f268SJie Qiu #define I2S_UV_U BIT(1) 258f83f268SJie Qiu #define I2S_UV_CH_EN_MASK 0x3c 268f83f268SJie Qiu #define I2S_UV_CH_EN(x) BIT((x) + 2) 278f83f268SJie Qiu #define I2S_UV_TMDS_DEBUG BIT(6) 288f83f268SJie Qiu #define I2S_UV_NORMAL_INFO_INV BIT(7) 298f83f268SJie Qiu #define GRL_ACP_ISRC_CTRL 0x158 308f83f268SJie Qiu #define VS_EN BIT(0) 318f83f268SJie Qiu #define ACP_EN BIT(1) 328f83f268SJie Qiu #define ISRC1_EN BIT(2) 338f83f268SJie Qiu #define ISRC2_EN BIT(3) 348f83f268SJie Qiu #define GAMUT_EN BIT(4) 358f83f268SJie Qiu #define GRL_CTS_CTRL 0x160 368f83f268SJie Qiu #define CTS_CTRL_SOFT BIT(0) 378f83f268SJie Qiu #define GRL_INT 0x14 388f83f268SJie Qiu #define INT_MDI BIT(0) 398f83f268SJie Qiu #define INT_HDCP BIT(1) 408f83f268SJie Qiu #define INT_FIFO_O BIT(2) 418f83f268SJie Qiu #define INT_FIFO_U BIT(3) 428f83f268SJie Qiu #define INT_IFM_ERR BIT(4) 438f83f268SJie Qiu #define INT_INF_DONE BIT(5) 448f83f268SJie Qiu #define INT_NCTS_DONE BIT(6) 458f83f268SJie Qiu #define INT_CTRL_PKT_DONE BIT(7) 468f83f268SJie Qiu #define GRL_INT_MASK 0x18 478f83f268SJie Qiu #define GRL_CTRL 0x1C 488f83f268SJie Qiu #define CTRL_GEN_EN BIT(2) 498f83f268SJie Qiu #define CTRL_SPD_EN BIT(3) 508f83f268SJie Qiu #define CTRL_MPEG_EN BIT(4) 518f83f268SJie Qiu #define CTRL_AUDIO_EN BIT(5) 528f83f268SJie Qiu #define CTRL_AVI_EN BIT(6) 538f83f268SJie Qiu #define CTRL_AVMUTE BIT(7) 548f83f268SJie Qiu #define GRL_STATUS 0x20 558f83f268SJie Qiu #define STATUS_HTPLG BIT(0) 568f83f268SJie Qiu #define STATUS_PORD BIT(1) 578f83f268SJie Qiu #define GRL_DIVN 0x170 588f83f268SJie Qiu #define NCTS_WRI_ANYTIME BIT(6) 598f83f268SJie Qiu #define GRL_AUDIO_CFG 0x17C 608f83f268SJie Qiu #define AUDIO_ZERO BIT(0) 618f83f268SJie Qiu #define HIGH_BIT_RATE BIT(1) 628f83f268SJie Qiu #define SACD_DST BIT(2) 638f83f268SJie Qiu #define DST_NORMAL_DOUBLE BIT(3) 648f83f268SJie Qiu #define DSD_INV BIT(4) 658f83f268SJie Qiu #define LR_INV BIT(5) 668f83f268SJie Qiu #define LR_MIX BIT(6) 678f83f268SJie Qiu #define DSD_SEL BIT(7) 688f83f268SJie Qiu #define GRL_NCTS 0x184 698f83f268SJie Qiu #define GRL_CH_SW0 0x18C 708f83f268SJie Qiu #define GRL_CH_SW1 0x190 718f83f268SJie Qiu #define GRL_CH_SW2 0x194 728f83f268SJie Qiu #define CH_SWITCH(from, to) ((from) << ((to) * 3)) 738f83f268SJie Qiu #define GRL_INFOFRM_VER 0x19C 748f83f268SJie Qiu #define GRL_INFOFRM_TYPE 0x1A0 758f83f268SJie Qiu #define GRL_INFOFRM_LNG 0x1A4 768f83f268SJie Qiu #define GRL_MIX_CTRL 0x1B4 778f83f268SJie Qiu #define MIX_CTRL_SRC_EN BIT(0) 788f83f268SJie Qiu #define BYPASS_VOLUME BIT(1) 798f83f268SJie Qiu #define MIX_CTRL_FLAT BIT(7) 808f83f268SJie Qiu #define GRL_AOUT_CFG 0x1C4 818f83f268SJie Qiu #define AOUT_BNUM_SEL_MASK 0x03 828f83f268SJie Qiu #define AOUT_24BIT 0x00 838f83f268SJie Qiu #define AOUT_20BIT 0x02 848f83f268SJie Qiu #define AOUT_16BIT 0x03 858f83f268SJie Qiu #define AOUT_FIFO_ADAP_CTRL BIT(6) 868f83f268SJie Qiu #define AOUT_BURST_PREAMBLE_EN BIT(7) 878f83f268SJie Qiu #define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \ 888f83f268SJie Qiu AOUT_FIFO_ADAP_CTRL) 898f83f268SJie Qiu #define GRL_SHIFT_L1 0x1C0 908f83f268SJie Qiu #define GRL_SHIFT_R2 0x1B0 918f83f268SJie Qiu #define AUDIO_PACKET_OFF BIT(6) 928f83f268SJie Qiu #define GRL_CFG0 0x24 938f83f268SJie Qiu #define CFG0_I2S_MODE_MASK 0x3 948f83f268SJie Qiu #define CFG0_I2S_MODE_RTJ 0x1 958f83f268SJie Qiu #define CFG0_I2S_MODE_LTJ 0x0 968f83f268SJie Qiu #define CFG0_I2S_MODE_I2S 0x2 978f83f268SJie Qiu #define CFG0_W_LENGTH_MASK 0x30 988f83f268SJie Qiu #define CFG0_W_LENGTH_24BIT 0x00 998f83f268SJie Qiu #define CFG0_W_LENGTH_16BIT 0x10 1008f83f268SJie Qiu #define GRL_CFG1 0x28 1018f83f268SJie Qiu #define CFG1_EDG_SEL BIT(0) 1028f83f268SJie Qiu #define CFG1_SPDIF BIT(1) 1038f83f268SJie Qiu #define CFG1_DVI BIT(2) 1048f83f268SJie Qiu #define CFG1_HDCP_DEBUG BIT(3) 1058f83f268SJie Qiu #define GRL_CFG2 0x2c 1068f83f268SJie Qiu #define CFG2_MHL_DE_SEL BIT(3) 1078f83f268SJie Qiu #define CFG2_MHL_FAKE_DE_SEL BIT(4) 1088f83f268SJie Qiu #define CFG2_MHL_DATA_REMAP BIT(5) 1098f83f268SJie Qiu #define CFG2_NOTICE_EN BIT(6) 1108f83f268SJie Qiu #define CFG2_ACLK_INV BIT(7) 1118f83f268SJie Qiu #define GRL_CFG3 0x30 1128f83f268SJie Qiu #define CFG3_AES_KEY_INDEX_MASK 0x3f 1138f83f268SJie Qiu #define CFG3_CONTROL_PACKET_DELAY BIT(6) 1148f83f268SJie Qiu #define CFG3_KSV_LOAD_START BIT(7) 1158f83f268SJie Qiu #define GRL_CFG4 0x34 1168f83f268SJie Qiu #define CFG4_AES_KEY_LOAD BIT(4) 1178f83f268SJie Qiu #define CFG4_AV_UNMUTE_EN BIT(5) 1188f83f268SJie Qiu #define CFG4_AV_UNMUTE_SET BIT(6) 1198f83f268SJie Qiu #define CFG4_MHL_MODE BIT(7) 1208f83f268SJie Qiu #define GRL_CFG5 0x38 1218f83f268SJie Qiu #define CFG5_CD_RATIO_MASK 0x8F 1228f83f268SJie Qiu #define CFG5_FS128 (0x1 << 4) 1238f83f268SJie Qiu #define CFG5_FS256 (0x2 << 4) 1248f83f268SJie Qiu #define CFG5_FS384 (0x3 << 4) 1258f83f268SJie Qiu #define CFG5_FS512 (0x4 << 4) 1268f83f268SJie Qiu #define CFG5_FS768 (0x6 << 4) 1278f83f268SJie Qiu #define DUMMY_304 0x304 1288f83f268SJie Qiu #define CHMO_SEL (0x3 << 2) 1298f83f268SJie Qiu #define CHM1_SEL (0x3 << 4) 1308f83f268SJie Qiu #define CHM2_SEL (0x3 << 6) 1318f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL BIT(1) 1328f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL_64 (1 << 1) 1338f83f268SJie Qiu #define AUDIO_I2S_NCTS_SEL_128 (0 << 1) 1348f83f268SJie Qiu #define NEW_GCP_CTRL BIT(0) 1358f83f268SJie Qiu #define NEW_GCP_CTRL_MERGE BIT(0) 1368f83f268SJie Qiu #define GRL_L_STATUS_0 0x200 1378f83f268SJie Qiu #define GRL_L_STATUS_1 0x204 1388f83f268SJie Qiu #define GRL_L_STATUS_2 0x208 1398f83f268SJie Qiu #define GRL_L_STATUS_3 0x20c 1408f83f268SJie Qiu #define GRL_L_STATUS_4 0x210 1418f83f268SJie Qiu #define GRL_L_STATUS_5 0x214 1428f83f268SJie Qiu #define GRL_L_STATUS_6 0x218 1438f83f268SJie Qiu #define GRL_L_STATUS_7 0x21c 1448f83f268SJie Qiu #define GRL_L_STATUS_8 0x220 1458f83f268SJie Qiu #define GRL_L_STATUS_9 0x224 1468f83f268SJie Qiu #define GRL_L_STATUS_10 0x228 1478f83f268SJie Qiu #define GRL_L_STATUS_11 0x22c 1488f83f268SJie Qiu #define GRL_L_STATUS_12 0x230 1498f83f268SJie Qiu #define GRL_L_STATUS_13 0x234 1508f83f268SJie Qiu #define GRL_L_STATUS_14 0x238 1518f83f268SJie Qiu #define GRL_L_STATUS_15 0x23c 1528f83f268SJie Qiu #define GRL_L_STATUS_16 0x240 1538f83f268SJie Qiu #define GRL_L_STATUS_17 0x244 1548f83f268SJie Qiu #define GRL_L_STATUS_18 0x248 1558f83f268SJie Qiu #define GRL_L_STATUS_19 0x24c 1568f83f268SJie Qiu #define GRL_L_STATUS_20 0x250 1578f83f268SJie Qiu #define GRL_L_STATUS_21 0x254 1588f83f268SJie Qiu #define GRL_L_STATUS_22 0x258 1598f83f268SJie Qiu #define GRL_L_STATUS_23 0x25c 1608f83f268SJie Qiu #define GRL_R_STATUS_0 0x260 1618f83f268SJie Qiu #define GRL_R_STATUS_1 0x264 1628f83f268SJie Qiu #define GRL_R_STATUS_2 0x268 1638f83f268SJie Qiu #define GRL_R_STATUS_3 0x26c 1648f83f268SJie Qiu #define GRL_R_STATUS_4 0x270 1658f83f268SJie Qiu #define GRL_R_STATUS_5 0x274 1668f83f268SJie Qiu #define GRL_R_STATUS_6 0x278 1678f83f268SJie Qiu #define GRL_R_STATUS_7 0x27c 1688f83f268SJie Qiu #define GRL_R_STATUS_8 0x280 1698f83f268SJie Qiu #define GRL_R_STATUS_9 0x284 1708f83f268SJie Qiu #define GRL_R_STATUS_10 0x288 1718f83f268SJie Qiu #define GRL_R_STATUS_11 0x28c 1728f83f268SJie Qiu #define GRL_R_STATUS_12 0x290 1738f83f268SJie Qiu #define GRL_R_STATUS_13 0x294 1748f83f268SJie Qiu #define GRL_R_STATUS_14 0x298 1758f83f268SJie Qiu #define GRL_R_STATUS_15 0x29c 1768f83f268SJie Qiu #define GRL_R_STATUS_16 0x2a0 1778f83f268SJie Qiu #define GRL_R_STATUS_17 0x2a4 1788f83f268SJie Qiu #define GRL_R_STATUS_18 0x2a8 1798f83f268SJie Qiu #define GRL_R_STATUS_19 0x2ac 1808f83f268SJie Qiu #define GRL_R_STATUS_20 0x2b0 1818f83f268SJie Qiu #define GRL_R_STATUS_21 0x2b4 1828f83f268SJie Qiu #define GRL_R_STATUS_22 0x2b8 1838f83f268SJie Qiu #define GRL_R_STATUS_23 0x2bc 1848f83f268SJie Qiu #define GRL_ABIST_CTRL0 0x2D4 1858f83f268SJie Qiu #define GRL_ABIST_CTRL1 0x2D8 1868f83f268SJie Qiu #define ABIST_EN BIT(7) 1878f83f268SJie Qiu #define ABIST_DATA_FMT (0x7 << 0) 1888f83f268SJie Qiu #define VIDEO_CFG_0 0x380 1898f83f268SJie Qiu #define VIDEO_CFG_1 0x384 1908f83f268SJie Qiu #define VIDEO_CFG_2 0x388 1918f83f268SJie Qiu #define VIDEO_CFG_3 0x38c 1928f83f268SJie Qiu #define VIDEO_CFG_4 0x390 1938f83f268SJie Qiu #define VIDEO_SOURCE_SEL BIT(7) 1948f83f268SJie Qiu #define NORMAL_PATH (1 << 7) 1958f83f268SJie Qiu #define GEN_RGB (0 << 7) 1968f83f268SJie Qiu 1978f83f268SJie Qiu #define HDMI_SYS_CFG1C 0x000 1988f83f268SJie Qiu #define HDMI_ON BIT(0) 1998f83f268SJie Qiu #define HDMI_RST BIT(1) 2008f83f268SJie Qiu #define ANLG_ON BIT(2) 2018f83f268SJie Qiu #define CFG10_DVI BIT(3) 2028f83f268SJie Qiu #define HDMI_TST BIT(3) 2038f83f268SJie Qiu #define SYS_KEYMASK1 (0xff << 8) 2048f83f268SJie Qiu #define SYS_KEYMASK2 (0xff << 16) 2058f83f268SJie Qiu #define AUD_OUTSYNC_EN BIT(24) 2068f83f268SJie Qiu #define AUD_OUTSYNC_PRE_EN BIT(25) 2078f83f268SJie Qiu #define I2CM_ON BIT(26) 2088f83f268SJie Qiu #define E2PROM_TYPE_8BIT BIT(27) 2098f83f268SJie Qiu #define MCM_E2PROM_ON BIT(28) 2108f83f268SJie Qiu #define EXT_E2PROM_ON BIT(29) 2118f83f268SJie Qiu #define HTPLG_PIN_SEL_OFF BIT(30) 2128f83f268SJie Qiu #define AES_EFUSE_ENABLE BIT(31) 2138f83f268SJie Qiu #define HDMI_SYS_CFG20 0x004 2148f83f268SJie Qiu #define DEEP_COLOR_MODE_MASK (3 << 1) 2158f83f268SJie Qiu #define COLOR_8BIT_MODE (0 << 1) 2168f83f268SJie Qiu #define COLOR_10BIT_MODE (1 << 1) 2178f83f268SJie Qiu #define COLOR_12BIT_MODE (2 << 1) 2188f83f268SJie Qiu #define COLOR_16BIT_MODE (3 << 1) 2198f83f268SJie Qiu #define DEEP_COLOR_EN BIT(0) 2208f83f268SJie Qiu #define HDMI_AUDIO_TEST_SEL BIT(8) 2218f83f268SJie Qiu #define HDMI2P0_EN BIT(11) 2228f83f268SJie Qiu #define HDMI_OUT_FIFO_EN BIT(16) 2238f83f268SJie Qiu #define HDMI_OUT_FIFO_CLK_INV BIT(17) 2248f83f268SJie Qiu #define MHL_MODE_ON BIT(28) 2258f83f268SJie Qiu #define MHL_PP_MODE BIT(29) 2268f83f268SJie Qiu #define MHL_SYNC_AUTO_EN BIT(30) 2278f83f268SJie Qiu #define HDMI_PCLK_FREE_RUN BIT(31) 2288f83f268SJie Qiu 22956ba355dSJie Qiu #define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 2308f83f268SJie Qiu #endif 231