Lines Matching +full:7 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
26 #define ADF4377_0000_SOFT_RESET_R_MSK BIT(7)
27 #define ADF4377_0000_LSB_FIRST_R_MSK BIT(6)
28 #define ADF4377_0000_ADDRESS_ASC_R_MSK BIT(5)
29 #define ADF4377_0000_SDO_ACTIVE_R_MSK BIT(4)
30 #define ADF4377_0000_SDO_ACTIVE_MSK BIT(3)
31 #define ADF4377_0000_ADDRESS_ASC_MSK BIT(2)
32 #define ADF4377_0000_LSB_FIRST_MSK BIT(1)
33 #define ADF4377_0000_SOFT_RESET_MSK BIT(0)
35 /* ADF4377 REG0000 Bit Definition */
49 #define ADF4377_0001_SINGLE_INSTR_MSK BIT(7)
50 #define ADF4377_0001_MASTER_RB_CTRL_MSK BIT(5)
52 /* ADF4377 REG0003 Bit Definition */
55 /* ADF4377 REG0004 Bit Definition */
58 /* ADF4377 REG0005 Bit Definition */
62 #define ADF4377_000A_SCRATCHPAD_MSK GENMASK(7, 0)
64 /* ADF4377 REG000C Bit Definition */
67 /* ADF4377 REG000D Bit Definition */
70 /* ADF4377 REG000F Bit Definition */
71 #define ADF4377_000F_R00F_RSV1_MSK GENMASK(7, 0)
74 #define ADF4377_0010_N_INT_LSB_MSK GENMASK(7, 0)
77 #define ADF4377_0011_EN_AUTOCAL_MSK BIT(7)
78 #define ADF4377_0011_EN_RDBLR_MSK BIT(6)
82 /* ADF4377 REG0011 Bit Definition */
89 #define ADF4377_0012_CLKOUT_DIV_MSK GENMASK(7, 6)
92 /* ADF4377 REG0012 Bit Definition */
102 /* ADF4377 REG0013 Bit Definition */
109 #define ADF4377_0014_M_VCO_BAND_MSK GENMASK(7, 0)
112 #define ADF4377_0015_BLEED_I_LSB_MSK GENMASK(7, 6)
113 #define ADF4377_0015_BLEED_POL_MSK BIT(5)
114 #define ADF4377_0015_EN_BLEED_MSK BIT(4)
117 /* ADF4377 REG0015 Bit Definition */
139 #define ADF4377_0016_BLEED_I_MSB_MSK GENMASK(7, 0)
142 #define ADF4377_0016_INV_CLKOUT_MSK BIT(7)
146 #define ADF4377_0018_CMOS_OV_MSK BIT(7)
149 /* ADF4377 REG0018 Bit Definition */
154 #define ADF4377_0019_CLKOUT2_OP_MSK GENMASK(7, 6)
156 #define ADF4377_0019_PD_CLK_MSK BIT(3)
157 #define ADF4377_0019_PD_RDET_MSK BIT(2)
158 #define ADF4377_0019_PD_ADC_MSK BIT(1)
159 #define ADF4377_0019_PD_CALADC_MSK BIT(0)
161 /* ADF4377 REG0019 Bit Definition */
168 #define ADF4377_001A_PD_ALL_MSK BIT(7)
169 #define ADF4377_001A_PD_RDIV_MSK BIT(6)
170 #define ADF4377_001A_PD_NDIV_MSK BIT(5)
171 #define ADF4377_001A_PD_VCO_MSK BIT(4)
172 #define ADF4377_001A_PD_LD_MSK BIT(3)
173 #define ADF4377_001A_PD_PFDCP_MSK BIT(2)
174 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1)
175 #define ADF4377_001A_PD_CLKOUT2_MSK BIT(0)
178 #define ADF4377_001B_EN_LOL_MSK BIT(7)
179 #define ADF4377_001B_LDWIN_PW_MSK BIT(6)
180 #define ADF4377_001B_EN_LDWIN_MSK BIT(5)
183 /* ADF4377 REG001B Bit Definition */
188 #define ADF4377_001C_EN_DNCLK_MSK BIT(7)
189 #define ADF4377_001C_EN_DRCLK_MSK BIT(6)
190 #define ADF4377_001C_RST_LD_MSK BIT(2)
191 #define ADF4377_001C_R01C_RSV1_MSK BIT(0)
193 /* ADF4377 REG001C Bit Definition */
200 #define ADF4377_001D_MUXOUT_MSK GENMASK(7, 4)
201 #define ADF4377_001D_EN_CPTEST_MSK BIT(2)
202 #define ADF4377_001D_CP_DOWN_MSK BIT(1)
203 #define ADF4377_001D_CP_UP_MSK BIT(0)
215 #define ADF4377_001F_BST_REF_MSK BIT(7)
216 #define ADF4377_001F_FILT_REF_MSK BIT(6)
217 #define ADF4377_001F_REF_SEL_MSK BIT(5)
220 /* ADF4377 REG001F Bit Definition */
233 #define ADF4377_0020_RST_SYS_MSK BIT(4)
234 #define ADF4377_0020_EN_ADC_CLK_MSK BIT(3)
235 #define ADF4377_0020_R020_RSV1_MSK BIT(0)
237 /* ADF4377 REG0021 Bit Definition */
240 /* ADF4377 REG0022 Bit Definition */
244 #define ADF4377_0023_CAT_CT_SEL BIT(7)
247 /* ADF4377 REG0023 Bit Definition */
251 #define ADF4377_0024_DCLK_MODE_MSK BIT(2)
254 #define ADF4377_0025_CLKODIV_DB_MSK BIT(7)
255 #define ADF4377_0025_DCLK_DB_MSK BIT(6)
258 /* ADF4377 REG0025 Bit Definition */
262 #define ADF4377_0026_VCO_BAND_DIV_MSK GENMASK(7, 0)
265 #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK GENMASK(7, 0)
268 #define ADF4377_0028_O_VCO_DB_MSK BIT(7)
272 #define ADF4377_0029_VCO_ALC_TO_LSB_MSK GENMASK(7, 0)
275 #define ADF4377_002A_DEL_CTRL_DB_MSK BIT(7)
282 #define ADF4377_002D_ADC_CLK_DIV_MSK GENMASK(7, 0)
285 #define ADF4377_002E_EN_ADC_CNV_MSK BIT(7)
286 #define ADF4377_002E_EN_ADC_MSK BIT(1)
287 #define ADF4377_002E_ADC_A_CONV_MSK BIT(0)
289 /* ADF4377 REG002E Bit Definition */
296 /* ADF4377 REG002F Bit Definition */
302 /* ADF4377 REG0031 Bit Definition */
306 #define ADF4377_0032_ADC_CLK_SEL_MSK BIT(6)
309 /* ADF4377 REG0032 Bit Definition */
315 /* ADF4377 REG0033 Bit Definition */
318 /* ADF4377 REG0034 Bit Definition */
321 /* ADF4377 REG003A Bit Definition */
324 /* ADF4377 REG003B Bit Definition */
328 #define ADF4377_003D_O_VCO_BAND_MSK BIT(3)
329 #define ADF4377_003D_O_VCO_CORE_MSK BIT(2)
330 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1)
332 /* ADF4377 REG003D Bit Definition */
346 #define ADF4377_0045_ADC_ST_CNV_MSK BIT(0)
349 #define ADF4377_0049_EN_CLK2_MSK BIT(7)
350 #define ADF4377_0049_EN_CLK1_MSK BIT(6)
351 #define ADF4377_0049_REF_OK_MSK BIT(3)
352 #define ADF4377_0049_ADC_BUSY_MSK BIT(2)
353 #define ADF4377_0049_FSM_BUSY_MSK BIT(1)
354 #define ADF4377_0049_LOCKED_MSK BIT(0)
360 #define ADF4377_004C_CHIP_TEMP_LSB_MSK GENMASK(7, 0)
363 #define ADF4377_004D_CHIP_TEMP_MSB_MSK BIT(0)
366 #define ADF4377_004F_VCO_BAND_MSK GENMASK(7, 0)
372 #define ADF4377_0054_CHIP_VERSION_MSK GENMASK(7, 0)
375 #define ADF4377_SPI_READ_CMD BIT(7)
470 .read_flag_mask = BIT(7),
482 return regmap_read(st->regmap, reg, read_val); in adf4377_reg_access()
484 return regmap_write(st->regmap, reg, write_val); in adf4377_reg_access()
496 ret = regmap_update_bits(st->regmap, 0x0, ADF4377_0000_SOFT_RESET_MSK | in adf4377_soft_reset()
503 return regmap_read_poll_timeout(st->regmap, 0x0, read_val, in adf4377_soft_reset()
514 mutex_lock(&st->lock); in adf4377_get_freq()
515 ret = regmap_read(st->regmap, 0x12, &ref_div_factor); in adf4377_get_freq()
519 ret = regmap_bulk_read(st->regmap, 0x10, st->buf, sizeof(st->buf)); in adf4377_get_freq()
523 clkin_freq = clk_get_rate(st->clkin); in adf4377_get_freq()
526 get_unaligned_le16(&st->buf)); in adf4377_get_freq()
530 mutex_unlock(&st->lock); in adf4377_get_freq()
541 mutex_lock(&st->lock); in adf4377_set_freq()
544 ret = -EINVAL; in adf4377_set_freq()
548 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | in adf4377_set_freq()
555 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_AUTOCAL_MSK | in adf4377_set_freq()
558 FIELD_PREP(ADF4377_0011_DCLK_DIV2_MSK, st->dclk_div2)); in adf4377_set_freq()
562 ret = regmap_update_bits(st->regmap, 0x2E, ADF4377_002E_EN_ADC_CNV_MSK | in adf4377_set_freq()
572 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, in adf4377_set_freq()
577 ret = regmap_update_bits(st->regmap, 0x2F, ADF4377_002F_DCLK_DIV1_MSK, in adf4377_set_freq()
578 FIELD_PREP(ADF4377_002F_DCLK_DIV1_MSK, st->dclk_div1)); in adf4377_set_freq()
582 ret = regmap_update_bits(st->regmap, 0x24, ADF4377_0024_DCLK_MODE_MSK, in adf4377_set_freq()
583 FIELD_PREP(ADF4377_0024_DCLK_MODE_MSK, st->dclk_mode)); in adf4377_set_freq()
587 ret = regmap_write(st->regmap, 0x27, in adf4377_set_freq()
589 st->synth_lock_timeout)); in adf4377_set_freq()
593 ret = regmap_update_bits(st->regmap, 0x28, ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK, in adf4377_set_freq()
595 st->synth_lock_timeout >> 8)); in adf4377_set_freq()
599 ret = regmap_write(st->regmap, 0x29, in adf4377_set_freq()
601 st->vco_alc_timeout)); in adf4377_set_freq()
605 ret = regmap_update_bits(st->regmap, 0x2A, ADF4377_002A_VCO_ALC_TO_MSB_MSK, in adf4377_set_freq()
607 st->vco_alc_timeout >> 8)); in adf4377_set_freq()
611 ret = regmap_write(st->regmap, 0x26, in adf4377_set_freq()
612 FIELD_PREP(ADF4377_0026_VCO_BAND_DIV_MSK, st->vco_band_div)); in adf4377_set_freq()
616 ret = regmap_write(st->regmap, 0x2D, in adf4377_set_freq()
617 FIELD_PREP(ADF4377_002D_ADC_CLK_DIV_MSK, st->adc_clk_div)); in adf4377_set_freq()
621 st->clkout_div_sel = 0; in adf4377_set_freq()
627 st->clkout_div_sel++; in adf4377_set_freq()
630 st->n_int = div_u64(freq, st->f_pfd); in adf4377_set_freq()
632 ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_RDBLR_MSK | in adf4377_set_freq()
635 FIELD_PREP(ADF4377_0011_N_INT_MSB_MSK, st->n_int >> 8)); in adf4377_set_freq()
639 ret = regmap_update_bits(st->regmap, 0x12, ADF4377_0012_R_DIV_MSK | in adf4377_set_freq()
641 FIELD_PREP(ADF4377_0012_CLKOUT_DIV_MSK, st->clkout_div_sel) | in adf4377_set_freq()
642 FIELD_PREP(ADF4377_0012_R_DIV_MSK, st->ref_div_factor)); in adf4377_set_freq()
646 ret = regmap_write(st->regmap, 0x10, in adf4377_set_freq()
647 FIELD_PREP(ADF4377_0010_N_INT_LSB_MSK, st->n_int)); in adf4377_set_freq()
651 ret = regmap_read_poll_timeout(st->regmap, 0x49, read_val, in adf4377_set_freq()
657 ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK | in adf4377_set_freq()
665 ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK, in adf4377_set_freq()
671 ret = regmap_update_bits(st->regmap, 0x19, ADF4377_0019_CLKOUT2_OP_MSK | in adf4377_set_freq()
679 mutex_unlock(&st->lock); in adf4377_set_freq()
686 if (st->gpio_ce) { in adf4377_gpio_init()
687 gpiod_set_value(st->gpio_ce, 1); in adf4377_gpio_init()
689 /* Delay for SPI register bits to settle to their power-on reset state */ in adf4377_gpio_init()
693 if (st->gpio_enclk1) in adf4377_gpio_init()
694 gpiod_set_value(st->gpio_enclk1, 1); in adf4377_gpio_init()
696 if (st->gpio_enclk2) in adf4377_gpio_init()
697 gpiod_set_value(st->gpio_enclk2, 1); in adf4377_gpio_init()
702 struct spi_device *spi = st->spi; in adf4377_init()
709 dev_err(&spi->dev, "Failed to soft reset.\n"); in adf4377_init()
713 ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults, in adf4377_init()
716 dev_err(&spi->dev, "Failed to set default registers.\n"); in adf4377_init()
720 ret = regmap_update_bits(st->regmap, 0x00, in adf4377_init()
727 dev_err(&spi->dev, "Failed to set 4-Wire Operation.\n"); in adf4377_init()
731 st->clkin_freq = clk_get_rate(st->clkin); in adf4377_init()
734 ret = regmap_write(st->regmap, 0x1a, in adf4377_init()
744 dev_err(&spi->dev, "Failed to set power down registers.\n"); in adf4377_init()
749 ret = regmap_update_bits(st->regmap, 0x1D, in adf4377_init()
751 FIELD_PREP(ADF4377_001D_MUXOUT_MSK, st->muxout_select)); in adf4377_init()
756 st->ref_div_factor = 0; in adf4377_init()
758 st->ref_div_factor++; in adf4377_init()
759 st->f_pfd = st->clkin_freq / st->ref_div_factor; in adf4377_init()
760 } while (st->f_pfd > ADF4377_MAX_FREQ_PFD); in adf4377_init()
762 if (st->f_pfd > ADF4377_MAX_FREQ_PFD || st->f_pfd < ADF4377_MIN_FREQ_PFD) in adf4377_init()
763 return -EINVAL; in adf4377_init()
765 st->f_div_rclk = st->f_pfd; in adf4377_init()
767 if (st->f_pfd <= ADF4377_FREQ_PFD_80MHZ) { in adf4377_init()
768 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; in adf4377_init()
769 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; in adf4377_init()
770 st->dclk_mode = 0; in adf4377_init()
771 } else if (st->f_pfd <= ADF4377_FREQ_PFD_125MHZ) { in adf4377_init()
772 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1; in adf4377_init()
773 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; in adf4377_init()
774 st->dclk_mode = 1; in adf4377_init()
775 } else if (st->f_pfd <= ADF4377_FREQ_PFD_160MHZ) { in adf4377_init()
776 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; in adf4377_init()
777 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; in adf4377_init()
778 st->dclk_mode = 0; in adf4377_init()
779 st->f_div_rclk /= 2; in adf4377_init()
780 } else if (st->f_pfd <= ADF4377_FREQ_PFD_250MHZ) { in adf4377_init()
781 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; in adf4377_init()
782 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1; in adf4377_init()
783 st->dclk_mode = 1; in adf4377_init()
784 st->f_div_rclk /= 2; in adf4377_init()
785 } else if (st->f_pfd <= ADF4377_FREQ_PFD_320MHZ) { in adf4377_init()
786 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; in adf4377_init()
787 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; in adf4377_init()
788 st->dclk_mode = 0; in adf4377_init()
789 st->f_div_rclk /= 4; in adf4377_init()
791 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2; in adf4377_init()
792 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2; in adf4377_init()
793 st->dclk_mode = 1; in adf4377_init()
794 st->f_div_rclk /= 4; in adf4377_init()
797 st->synth_lock_timeout = DIV_ROUND_UP(st->f_div_rclk, 50000); in adf4377_init()
798 st->vco_alc_timeout = DIV_ROUND_UP(st->f_div_rclk, 20000); in adf4377_init()
799 st->vco_band_div = DIV_ROUND_UP(st->f_div_rclk, 150000 * 16 * (1 << st->dclk_mode)); in adf4377_init()
800 st->adc_clk_div = DIV_ROUND_UP((st->f_div_rclk / 400000 - 2), 4); in adf4377_init()
820 return -EINVAL; in adf4377_read()
844 return -EINVAL; in adf4377_write()
878 struct spi_device *spi = st->spi; in adf4377_properties_parse()
881 st->clkin = devm_clk_get_enabled(&spi->dev, "ref_in"); in adf4377_properties_parse()
882 if (IS_ERR(st->clkin)) in adf4377_properties_parse()
883 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), in adf4377_properties_parse()
886 st->gpio_ce = devm_gpiod_get_optional(&st->spi->dev, "chip-enable", in adf4377_properties_parse()
888 if (IS_ERR(st->gpio_ce)) in adf4377_properties_parse()
889 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_ce), in adf4377_properties_parse()
892 st->gpio_enclk1 = devm_gpiod_get_optional(&st->spi->dev, "clk1-enable", in adf4377_properties_parse()
894 if (IS_ERR(st->gpio_enclk1)) in adf4377_properties_parse()
895 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk1), in adf4377_properties_parse()
898 if (st->chip_info->has_gpio_enclk2) { in adf4377_properties_parse()
899 st->gpio_enclk2 = devm_gpiod_get_optional(&st->spi->dev, "clk2-enable", in adf4377_properties_parse()
901 if (IS_ERR(st->gpio_enclk2)) in adf4377_properties_parse()
902 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk2), in adf4377_properties_parse()
906 ret = device_property_match_property_string(&spi->dev, "adi,muxout-select", in adf4377_properties_parse()
910 st->muxout_select = ret; in adf4377_properties_parse()
912 st->muxout_select = ADF4377_MUXOUT_HIGH_Z; in adf4377_properties_parse()
923 mutex_lock(&st->lock); in adf4377_freq_change()
925 mutex_unlock(&st->lock); in adf4377_freq_change()
949 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in adf4377_probe()
951 return -ENOMEM; in adf4377_probe()
959 indio_dev->info = &adf4377_info; in adf4377_probe()
960 indio_dev->name = "adf4377"; in adf4377_probe()
961 indio_dev->channels = adf4377_channels; in adf4377_probe()
962 indio_dev->num_channels = ARRAY_SIZE(adf4377_channels); in adf4377_probe()
964 st->regmap = regmap; in adf4377_probe()
965 st->spi = spi; in adf4377_probe()
966 st->chip_info = spi_get_device_match_data(spi); in adf4377_probe()
967 mutex_init(&st->lock); in adf4377_probe()
973 st->nb.notifier_call = adf4377_freq_change; in adf4377_probe()
974 ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb); in adf4377_probe()
982 return devm_iio_device_register(&spi->dev, indio_dev); in adf4377_probe()