Lines Matching +full:7 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
182 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
183 BUS_MSTOP(11, BIT(13))),
185 BUS_MSTOP(11, BIT(14))),
187 BUS_MSTOP(11, BIT(15))),
189 BUS_MSTOP(12, BIT(0))),
191 BUS_MSTOP(3, BIT(10))),
193 BUS_MSTOP(3, BIT(10))),
195 BUS_MSTOP(1, BIT(0))),
197 BUS_MSTOP(1, BIT(0))),
199 BUS_MSTOP(5, BIT(12))),
201 BUS_MSTOP(5, BIT(12))),
203 BUS_MSTOP(5, BIT(13))),
205 BUS_MSTOP(5, BIT(13))),
207 BUS_MSTOP(3, BIT(14))),
209 BUS_MSTOP(10, BIT(15))),
211 BUS_MSTOP(10, BIT(15))),
213 BUS_MSTOP(10, BIT(15))),
215 BUS_MSTOP(3, BIT(13))),
217 BUS_MSTOP(1, BIT(1))),
219 BUS_MSTOP(1, BIT(2))),
221 BUS_MSTOP(1, BIT(3))),
222 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
223 BUS_MSTOP(1, BIT(4))),
225 BUS_MSTOP(1, BIT(5))),
227 BUS_MSTOP(1, BIT(6))),
229 BUS_MSTOP(1, BIT(7))),
231 BUS_MSTOP(1, BIT(8))),
233 BUS_MSTOP(4, BIT(5))),
235 BUS_MSTOP(4, BIT(5))),
237 BUS_MSTOP(4, BIT(5))),
239 BUS_MSTOP(8, BIT(2))),
241 BUS_MSTOP(8, BIT(2))),
243 BUS_MSTOP(8, BIT(2))),
245 BUS_MSTOP(8, BIT(2))),
246 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
247 BUS_MSTOP(8, BIT(3))),
249 BUS_MSTOP(8, BIT(3))),
251 BUS_MSTOP(8, BIT(3))),
253 BUS_MSTOP(8, BIT(3))),
255 BUS_MSTOP(8, BIT(4))),
257 BUS_MSTOP(8, BIT(4))),
259 BUS_MSTOP(8, BIT(4))),
261 BUS_MSTOP(8, BIT(4))),
263 BUS_MSTOP(7, BIT(7))),
265 BUS_MSTOP(7, BIT(9))),
267 BUS_MSTOP(7, BIT(10))),
269 BUS_MSTOP(8, BIT(5)), 1),
271 BUS_MSTOP(8, BIT(5)), 1),
273 BUS_MSTOP(8, BIT(5)), 1),
275 BUS_MSTOP(8, BIT(5)), 1),
277 BUS_MSTOP(8, BIT(5))),
279 BUS_MSTOP(8, BIT(5))),
281 BUS_MSTOP(8, BIT(6)), 1),
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
287 BUS_MSTOP(8, BIT(6)), 1),
289 BUS_MSTOP(8, BIT(6))),
291 BUS_MSTOP(8, BIT(6))),
292 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
293 BUS_MSTOP(3, BIT(4))),
294 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
295 BUS_MSTOP(3, BIT(4))),
296 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
297 BUS_MSTOP(3, BIT(4))),
307 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
308 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
309 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
310 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
311 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
312 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
313 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
314 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
315 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
317 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
318 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
330 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */