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/linux/sound/soc/codecs/
H A Dmt6359.h140 #define AUXADC_RQST_CH0_MASK 0x1
141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
172 #define RG_ACCDET_CK_PDN_MASK 0x1
173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
[all …]
H A Drt5677.h298 #define RT5677_L_MUTE (0x1 << 15)
300 #define RT5677_VOL_L_MUTE (0x1 << 14)
302 #define RT5677_R_MUTE (0x1 << 7)
304 #define RT5677_VOL_R_MUTE (0x1 << 6)
312 #define RT5677_LOUT1_L_MUTE (0x1 << 15)
314 #define RT5677_LOUT1_L_DF (0x1 << 14)
316 #define RT5677_LOUT2_L_MUTE (0x1 << 13)
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
320 #define RT5677_LOUT3_L_MUTE (0x1 << 11)
322 #define RT5677_LOUT3_L_DF (0x1 << 10)
[all …]
H A Drt5682s.h412 #define RT5682S_L_MUTE (0x1 << 15)
414 #define RT5682S_R_MUTE (0x1 << 7)
419 #define RT5682S_CLK_SRC_PLL1 (0x1)
425 #define RT5682S_HPO_L_PATH_MASK (0x1 << 14)
426 #define RT5682S_HPO_L_PATH_EN (0x1 << 14)
428 #define RT5682S_HPO_R_PATH_MASK (0x1 << 13)
429 #define RT5682S_HPO_R_PATH_EN (0x1 << 13)
431 #define RT5682S_HPO_SEL_IP_EN_SW (0x1)
432 #define RT5682S_HPO_IP_EN_GATING (0x1)
442 #define RT5682S_EMB_JD_MASK (0x1 << 15)
[all …]
H A Drt5665.h431 #define RT5665_L_MUTE (0x1 << 15)
433 #define RT5665_VOL_L_MUTE (0x1 << 14)
435 #define RT5665_R_MUTE (0x1 << 7)
437 #define RT5665_VOL_R_MUTE (0x1 << 6)
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
459 #define RT5665_IN2_DF_MASK (0x1 << 7)
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
469 #define RT5665_IN4_DF_MASK (0x1 << 7)
481 #define RT5665_EMB_JD_EN (0x1 << 15)
483 #define RT5665_JD_MODE (0x1 << 13)
[all …]
H A Drt5668.h359 #define RT5668_L_MUTE (0x1 << 15)
361 #define RT5668_VOL_L_MUTE (0x1 << 14)
363 #define RT5668_R_MUTE (0x1 << 7)
365 #define RT5668_VOL_R_MUTE (0x1 << 6)
383 #define RT5668_EMB_JD_EN (0x1 << 15)
385 #define RT5668_EMB_JD_RST (0x1 << 14)
386 #define RT5668_JD_MODE (0x1 << 13)
388 #define RT5668_DET_TYPE (0x1 << 12)
390 #define RT5668_POLA_EXT_JD_MASK (0x1 << 11)
391 #define RT5668_POLA_EXT_JD_LOW (0x1 << 11)
[all …]
H A Drt5645.h217 #define RT5645_L_MUTE (0x1 << 15)
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
221 #define RT5645_R_MUTE (0x1 << 7)
223 #define RT5645_VOL_R_MUTE (0x1 << 6)
233 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
234 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
235 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
236 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
237 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
238 #define RT5645_CBJ_MIC_SW (0x1 <<
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H A Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
[all …]
H A Drt5616.h152 #define RT5616_L_MUTE (0x1 << 15)
154 #define RT5616_VOL_L_MUTE (0x1 << 14)
156 #define RT5616_R_MUTE (0x1 << 7)
158 #define RT5616_VOL_R_MUTE (0x1 << 6)
166 #define RT5616_EN_DFO (0x1 << 15)
174 #define RT5616_IN_DF1 (0x1 << 7)
176 #define RT5616_IN_DF2 (0x1 << 6)
182 #define RT5616_INR_SEL_MASK (0x1 << 7)
185 #define RT5616_INR_SEL_MONON (0x1 << 7)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
[all …]
H A Drt5659.h539 #define RT5659_L_MUTE (0x1 << 15)
541 #define RT5659_VOL_L_MUTE (0x1 << 14)
543 #define RT5659_R_MUTE (0x1 << 7)
545 #define RT5659_VOL_R_MUTE (0x1 << 6)
559 #define RT5659_IN1_DF_MASK (0x1 << 15)
567 #define RT5659_IN3_DF_MASK (0x1 << 15)
571 #define RT5659_IN4_DF_MASK (0x1 << 7)
583 #define RT5659_EMB_JD_EN (0x1 << 15)
585 #define RT5659_JD_MODE (0x1 << 13)
587 #define RT5659_EXT_JD_EN (0x1 << 11)
[all …]
H A Drt5640.h183 #define RT5640_L_MUTE (0x1 << 15)
185 #define RT5640_VOL_L_MUTE (0x1 << 14)
187 #define RT5640_R_MUTE (0x1 << 7)
189 #define RT5640_VOL_R_MUTE (0x1 << 6)
207 #define RT5640_IN_DF1 (0x1 << 7)
209 #define RT5640_IN_DF2 (0x1 << 6)
213 #define RT5640_INL_SEL_MASK (0x1 << 15)
216 #define RT5640_INL_SEL_MONOP (0x1 << 15)
219 #define RT5640_INR_SEL_MASK (0x1 << 7)
222 #define RT5640_INR_SEL_MONON (0x1 << 7)
[all …]
H A Drt5670.h213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_R_MUTE (0x1 << 7)
225 #define RT5670_ID_5672 (0x1 << 1)
231 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
232 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
233 #define RT5670_CBJ_BST1_EN (0x1 << 2)
236 #define RT5670_CBJ_MN_JD (0x1 << 12)
237 #define RT5670_CAPLESS_EN (0x1 << 11)
238 #define RT5670_CBJ_DET_MODE (0x1 << 7)
245 #define RT5670_IN_DF1 (0x1 << 7)
[all …]
H A Drk3328_codec.h30 #define PWR_RST_BYPASS_EN (0x1 << 6)
32 #define DIG_CORE_WORK (0x1 << 1)
34 #define SYS_WORK (0x1 << 0)
39 #define PIN_DIRECTION_OUT (0x1 << 5)
40 #define DAC_I2S_MODE_MASK BIT(4)
41 #define DAC_I2S_MODE_SLAVE (0x0 << 4)
42 #define DAC_I2S_MODE_MASTER (0x1 << 4)
47 #define DAC_I2S_LRP_REVERSAL (0x1 << 7)
50 #define DAC_VDL_20BITS (0x1 << 5)
53 #define DAC_MODE_MASK GENMASK(4, 3)
[all …]
H A Dda7219.h125 #define DA7219_SWITCH_EN_MAX 0x1
162 #define DA7219_I2C_TIMEOUT_EN_MASK (0x1 << 0)
166 #define DA7219_CIF_I2C_WRITE_MODE_MASK (0x1 << 0)
168 #define DA7219_CIF_REG_SOFT_RESET_MASK (0x1 << 7)
172 #define DA7219_SR_24_48_MASK (0x1 << 0)
197 #define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2)
202 #define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
206 #define DA7219_PLL_MODE_NORMAL (0x1 << 6)
224 #define DA7219_PLL_SRM_STATUS_SHIFT 4
225 #define DA7219_PLL_SRM_STATUS_MASK (0xF << 4)
[all …]
H A Drt5631.h83 #define RT5631_L_MUTE (0x1 << 15)
85 #define RT5631_L_EN (0x1 << 14)
87 #define RT5631_R_MUTE (0x1 << 7)
89 #define RT5631_R_EN (0x1 << 6)
96 #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14)
98 #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14)
99 #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6)
101 #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6)
104 #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14)
106 #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14)
[all …]
H A Dda7218.h22 #define DA7218_CIF_CTRL 0x1
212 #define DA7218_SWITCH_EN_MAX 0x1
216 #define DA7218_SYSTEM_ACTIVE_MASK (0x1 << 0)
218 /* DA7218_CIF_CTRL = 0x1 */
220 #define DA7218_CIF_I2C_WRITE_MODE_MASK (0x1 << 0)
233 #define DA7218_CHIP_MAJOR_SHIFT 4
234 #define DA7218_CHIP_MAJOR_MASK (0xF << 4)
246 #define DA7218_CIF_REG_SOFT_RESET_MASK (0x1 << 7)
251 #define DA7218_SR_DAC_SHIFT 4
252 #define DA7218_SR_DAC_MASK (0xF << 4)
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.h123 #define RESET_DP_TX (0x1 << 0)
126 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
131 #define AUD_FUNC_EN_N (0x1 << 3)
132 #define HDCP_FUNC_EN_N (0x1 << 2)
133 #define CRC_FUNC_EN_N (0x1 << 1)
134 #define SW_FUNC_EN_N (0x1 << 0)
[all …]
/linux/drivers/ipack/devices/
H A Dscc2698.h41 * The scc2698 contain 4 block.
86 #define MR1_CHRL_6_BITS (0x1 << 0)
89 #define MR1_PARITY_EVEN (0x1 << 2)
92 #define MR1_PARITY_FORCE (0x1 << 3)
96 #define MR1_ERROR_BLOCK (0x1 << 5)
98 #define MR1_RxINT_FFULL (0x1 << 6)
99 #define MR1_RxRTS_CONTROL_ON (0x1 << 7)
104 #define MR2_CTS_ENABLE_TX_ON (0x1 << 4)
105 #define MR2_CTS_ENABLE_TX_OFF (0x0 << 4)
106 #define MR2_TxRTS_CONTROL_ON (0x1 << 5)
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dcnic_defs.h17 #define L2_KWQE_OPCODE_VALUE_FLUSH (4)
63 #define L4_KCQE_COMPLETION_STATUS_NIC_ERROR (4)
73 #define L4_LAYER_CODE (4)
96 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
98 #define L4_KCQ_LAYER_CODE (0x7<<4)
99 #define L4_KCQ_LAYER_CODE_SHIFT 4
100 #define L4_KCQ_RESERVED4 (0x1<<7)
110 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
112 #define L4_KCQ_LAYER_CODE (0x7<<4)
113 #define L4_KCQ_LAYER_CODE_SHIFT 4
[all …]
/linux/arch/x86/crypto/
H A Dserpent-sse2-i586-asm_32.S3 * Serpent Cipher 4-way parallel algorithm (i586/SSE2)
17 #define arg_ctx 4
23 4-way SSE2 serpent
39 movd (4*(i)+(j))*4(CTX), t; \
42 #define K(x0, x1, x2, x3, x4, i) \ argument
47 pxor RT0, x1; \
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
57 pxor x0, x1; \
62 pxor x2, x1; \
63 movdqa x1, x4; \
[all …]
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \ argument
47 pxor x1, x3; \
48 pand x0, x1; \
49 pxor x4, x1; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
55 pand x1, x2; \
57 pxor RNOT, x1; \
59 pxor x2, x1;
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
62 movdqa x1, x4; \
[all …]
/linux/drivers/infiniband/hw/qedr/
H A Dqedr_hsi_rdma.h50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1
56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1
57 #define RDMA_CQE_RESPONDER_IMM_FLG_SHIFT 4
58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1
74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1
88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1
206 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
208 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1
210 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1
[all …]
/linux/include/linux/qed/
H A Dfcoe_common.h21 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
23 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
26 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
27 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
73 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
75 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
77 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
133 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
160 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
161 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h418 #define BCK_INVERSE_MASK 0x1
419 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
423 #define AWB2_ON_MASK 0x1
424 #define AWB2_ON_MASK_SFT (0x1 << 29)
426 #define VUL2_ON_MASK 0x1
427 #define VUL2_ON_MASK_SFT (0x1 << 27)
429 #define MOD_DAI_DUP_WR_MASK 0x1
430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
435 #define VUL12_R_MONO_MASK 0x1
436 #define VUL12_R_MONO_MASK_SFT (0x1 << 11)
[all …]
/linux/arch/arm64/include/asm/
H A Del2_setup.h30 mrs_s x1, SYS_ID_AA64MMFR4_EL1
31 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
32 cmp x1, #0
54 mov x1, #1 // Write something to FAR_EL1
55 msr far_el1, x1
57 mov x1, #2 // Try to overwrite it via FAR_EL2
58 msr far_el2, x1
60 mrs x1, far_el1 // If we see the latest write in FAR_EL1,
61 cmp x1, #2 // we can safely assume we are VHE only.
79 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
[all …]

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