Lines Matching +full:4 +full:x1
30 mrs_s x1, SYS_ID_AA64MMFR4_EL1
31 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
32 cmp x1, #0
54 mov x1, #1 // Write something to FAR_EL1
55 msr far_el1, x1
57 mov x1, #2 // Try to overwrite it via FAR_EL2
58 msr far_el2, x1
60 mrs x1, far_el1 // If we see the latest write in FAR_EL1,
61 cmp x1, #2 // we can safely assume we are VHE only.
79 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
84 mrs_s x1, SYS_ID_AA64PFR1_EL1
85 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
86 cbz x1, .Lset_hcrx_\@
113 __check_hvhe .LnVHE_\@, x1
123 ubfx \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
129 mrs x1, id_aa64dfr0_el1
130 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
132 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
155 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4
172 mrs x1, id_aa64mmfr1_el1
173 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
187 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4
204 ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4
252 mrs x1, mpidr_el1
254 msr vmpidr_el2, x1
259 __check_hvhe .LnVHE_\@, x1
282 mrs x1, id_aa64dfr0_el1
283 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
284 cbz x1, .Lskip_brbe_\@
293 mrs x1, id_aa64mmfr0_el1
294 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
295 cbz x1, .Lskip_fgt_\@
300 __spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1
306 mrs x1, id_aa64dfr0_el1
307 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
308 cbz x1, .Lskip_brbe_fgt_\@
341 mrs x1, id_aa64dfr0_el1
342 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
343 cbz x1, .Lskip_brbe_insn_fgt_\@
352 mrs x1, id_aa64pfr1_el1
353 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
354 cbz x1, .Lskip_sme_fgt_\@
361 mrs_s x1, SYS_ID_AA64MMFR3_EL1
362 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
363 cbz x1, .Lskip_pie_fgt_\@
370 mrs_s x1, SYS_ID_AA64MMFR3_EL1
371 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4
372 cbz x1, .Lskip_poe_fgt_\@
379 mrs_s x1, SYS_ID_AA64PFR1_EL1
380 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
381 cbz x1, .Lskip_gce_fgt_\@
394 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
395 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
396 cbz x1, .Lskip_amu_fgt_\@
406 mrs x1, id_aa64mmfr0_el1
407 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
408 cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2
412 mrs x1, id_aa64dfr0_el1
413 ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
414 cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9
422 __spe_vers_imp .Lskip_spefds_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x1
424 mrs_s x1, SYS_PMSIDR_EL1
425 and x1, x1, #PMSIDR_EL1_FDS
427 cbz x1, .Lskip_spefds_\@
446 * Regs: x0, x1 and x2 are clobbered.
487 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2
499 __check_override \idreg \fld 4 \pass \fail \tmp \ignore
504 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2
514 check_override id_aa64pfr1, ID_AA64PFR1_EL1_GCS_SHIFT, .Linit_gcs_\@, .Lskip_gcs_\@, x1, x2
521 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
524 __check_hvhe .Lcptr_nvhe_\@, x1
538 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
539 msr_s SYS_ZCR_EL2, x1 // length for EL1.
542 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
545 __check_hvhe .Lcptr_nvhe_sme_\@, x1
560 mrs x1, sctlr_el2
561 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
562 msr sctlr_el2, x1
568 mrs_s x1, SYS_ID_AA64SMFR0_EL1
569 …erride id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2
576 mrs_s x1, SYS_ID_AA64SMFR0_EL1
577 …_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1…
585 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
586 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
587 cbz x1, .Lskip_sme_\@