Lines Matching +full:4 +full:x1
412 #define RT5682S_L_MUTE (0x1 << 15)
414 #define RT5682S_R_MUTE (0x1 << 7)
419 #define RT5682S_CLK_SRC_PLL1 (0x1)
425 #define RT5682S_HPO_L_PATH_MASK (0x1 << 14)
426 #define RT5682S_HPO_L_PATH_EN (0x1 << 14)
428 #define RT5682S_HPO_R_PATH_MASK (0x1 << 13)
429 #define RT5682S_HPO_R_PATH_EN (0x1 << 13)
431 #define RT5682S_HPO_SEL_IP_EN_SW (0x1)
432 #define RT5682S_HPO_IP_EN_GATING (0x1)
442 #define RT5682S_EMB_JD_MASK (0x1 << 15)
443 #define RT5682S_EMB_JD_EN (0x1 << 15)
445 #define RT5682S_EMB_JD_RST (0x1 << 14)
446 #define RT5682S_JD_MODE (0x1 << 13)
448 #define RT5682S_DET_TYPE (0x1 << 12)
450 #define RT5682S_POLA_EXT_JD_MASK (0x1 << 11)
451 #define RT5682S_POLA_EXT_JD_LOW (0x1 << 11)
455 #define RT5682S_POL_FAST_OFF_MASK (0x1 << 8)
456 #define RT5682S_POL_FAST_OFF_HIGH (0x1 << 8)
458 #define RT5682S_FAST_OFF_MASK (0x1 << 7)
459 #define RT5682S_FAST_OFF_EN (0x1 << 7)
461 #define RT5682S_VREF_POW_MASK (0x1 << 6)
463 #define RT5682S_VREF_POW_REG (0x1 << 6)
465 #define RT5682S_MB1_PATH_MASK (0x1 << 5)
466 #define RT5682S_CTRL_MB1_REG (0x1 << 5)
468 #define RT5682S_MB2_PATH_BIT 4
469 #define RT5682S_MB2_PATH_MASK (0x1 << 4)
470 #define RT5682S_CTRL_MB2_REG (0x1 << 4)
471 #define RT5682S_CTRL_MB2_FSM (0x0 << 4)
472 #define RT5682S_TRIG_JD_MASK (0x1 << 3)
473 #define RT5682S_TRIG_JD_HIGH (0x1 << 3)
475 #define RT5682S_MIC_CAP_MASK (0x1 << 1)
476 #define RT5682S_MIC_CAP_HS (0x1 << 1)
478 #define RT5682S_MIC_CAP_SRC_MASK (0x1)
479 #define RT5682S_MIC_CAP_SRC_REG (0x1)
483 #define RT5682S_SEL_CBJ_TYPE_SLOW (0x1 << 15)
485 #define RT5682S_SEL_CBJ_TYPE_MASK (0x1 << 15)
486 #define RT5682S_POW_BG_MB1_MASK (0x1 << 13)
487 #define RT5682S_POW_BG_MB1_REG (0x1 << 13)
489 #define RT5682S_POW_BG_MB2_MASK (0x1 << 12)
490 #define RT5682S_POW_BG_MB2_REG (0x1 << 12)
492 #define RT5682S_EXT_JD_SRC (0x7 << 4)
493 #define RT5682S_EXT_JD_SRC_SFT 4
494 #define RT5682S_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
495 #define RT5682S_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
496 #define RT5682S_EXT_JD_SRC_JDH (0x2 << 4)
497 #define RT5682S_EXT_JD_SRC_JDL (0x3 << 4)
498 #define RT5682S_EXT_JD_SRC_MANUAL (0x4 << 4)
501 /* Combo Jack and Type Detection Control 4 (0x0012) */
502 #define RT5682S_CBJ_IN_BUF_MASK (0x1 << 7)
503 #define RT5682S_CBJ_IN_BUF_EN (0x1 << 7)
510 #define RT5682S_SEL_SHT_MID_TON_3 (0x1 << 12)
511 #define RT5682S_CBJ_JD_TEST_MASK (0x1 << 6)
513 #define RT5682S_CBJ_JD_TEST_MODE (0x1 << 6)
522 #define RT5682S_JD_FAST_OFF_SRC_GPIO2 (0x1 << 8)
544 #define RT5682S_ST_SRC_SEL (0x1 << 8)
546 #define RT5682S_ST_EN_MASK (0x1 << 6)
548 #define RT5682S_ST_EN (0x1 << 6)
552 #define RT5682S_M_STO1_ADC_L1 (0x1 << 15)
554 #define RT5682S_M_STO1_ADC_L2 (0x1 << 14)
556 #define RT5682S_STO1_ADC1L_SRC_MASK (0x1 << 13)
558 #define RT5682S_STO1_ADC1_SRC_ADC (0x1 << 13)
560 #define RT5682S_STO1_ADC2L_SRC_MASK (0x1 << 12)
564 #define RT5682S_M_STO1_ADC_R1 (0x1 << 7)
566 #define RT5682S_M_STO1_ADC_R2 (0x1 << 6)
568 #define RT5682S_STO1_ADC1R_SRC_MASK (0x1 << 5)
570 #define RT5682S_STO1_ADC2R_SRC_MASK (0x1 << 4)
571 #define RT5682S_STO1_ADC2R_SRC_SFT 4
576 #define RT5682S_M_ADCMIX_L (0x1 << 15)
578 #define RT5682S_M_DAC1_L (0x1 << 14)
580 #define RT5682S_M_ADCMIX_R (0x1 << 7)
582 #define RT5682S_M_DAC1_R (0x1 << 6)
586 #define RT5682S_M_DAC_L1_STO_L (0x1 << 15)
588 #define RT5682S_G_DAC_L1_STO_L_MASK (0x1 << 14)
590 #define RT5682S_M_DAC_R1_STO_L (0x1 << 13)
592 #define RT5682S_G_DAC_R1_STO_L_MASK (0x1 << 12)
594 #define RT5682S_M_DAC_L1_STO_R (0x1 << 7)
596 #define RT5682S_G_DAC_L1_STO_R_MASK (0x1 << 6)
598 #define RT5682S_M_DAC_R1_STO_R (0x1 << 5)
600 #define RT5682S_G_DAC_R1_STO_R_MASK (0x1 << 4)
601 #define RT5682S_G_DAC_R1_STO_R_SFT 4
604 #define RT5682S_M_ST_STO_L (0x1 << 9)
606 #define RT5682S_M_ST_STO_R (0x1 << 8)
608 #define RT5682S_DAC_L1_SRC_MASK (0x1 << 4)
609 #define RT5682S_A_DACL1_SFT 4
610 #define RT5682S_DAC_R1_SRC_MASK (0x1)
622 #define RT5682S_M_CBJ_RM1_L (0x1 << 7)
624 #define RT5682S_M_CBJ_RM1_R (0x1 << 6)
632 #define RT5682S_PWR_I2S1 (0x1 << 15)
634 #define RT5682S_PWR_I2S2 (0x1 << 14)
636 #define RT5682S_PRE_CHR_DAC_L1 (0x1 << 13)
638 #define RT5682S_PRE_CHR_DAC_R1 (0x1 << 12)
640 #define RT5682S_PWR_DAC_L1 (0x1 << 11)
642 #define RT5682S_PWR_DAC_R1 (0x1 << 10)
644 #define RT5682S_PWR_LDO (0x1 << 8)
646 #define RT5682S_PWR_D2S_L (0x1 << 7)
648 #define RT5682S_PWR_D2S_R (0x1 << 6)
650 #define RT5682S_PWR_ADC_L1 (0x1 << 4)
651 #define RT5682S_PWR_ADC_L1_BIT 4
652 #define RT5682S_PWR_ADC_R1 (0x1 << 3)
654 #define RT5682S_EFUSE_SW_EN (0x1 << 2)
656 #define RT5682S_PWR_EFUSE (0x1 << 1)
658 #define RT5682S_DIG_GATE_CTRL (0x1 << 0)
662 #define RT5682S_PWR_ADC_S1F (0x1 << 15)
664 #define RT5682S_PWR_DAC_S1F (0x1 << 10)
666 #define RT5682S_DLDO_I_LIMIT_MASK (0x1 << 7)
667 #define RT5682S_DLDO_I_LIMIT_EN (0x1 << 7)
669 #define RT5682S_DLDO_I_BIAS_SEL_4 (0x1 << 6)
671 #define RT5682S_DLDO_REG_TEST_1 (0x1 << 5)
673 #define RT5682S_DLDO_SRC_REG (0x1 << 4)
674 #define RT5682S_DLDO_SRC_EFUSE (0x0 << 4)
677 #define RT5682S_PWR_VREF1 (0x1 << 15)
679 #define RT5682S_PWR_FV1 (0x1 << 14)
681 #define RT5682S_PWR_VREF2 (0x1 << 13)
683 #define RT5682S_PWR_FV2 (0x1 << 12)
686 #define RT5682S_PWR_MB (0x1 << 9)
688 #define RT5682S_PWR_BG (0x1 << 7)
690 #define RT5682S_LDO1_BYPASS_MASK (0x1 << 6)
691 #define RT5682S_LDO1_BYPASS (0x1 << 6)
695 #define RT5682S_PWR_MCLK0_WD (0x1 << 15)
697 #define RT5682S_PWR_MCLK1_WD (0x1 << 14)
699 #define RT5682S_RST_MCLK0 (0x1 << 13)
701 #define RT5682S_RST_MCLK1 (0x1 << 12)
703 #define RT5682S_PWR_MB1 (0x1 << 11)
706 #define RT5682S_PWR_MB2 (0x1 << 10)
709 #define RT5682S_PWR_JD_MASK (0x1 << 0)
710 #define RT5682S_PWR_JD_ENABLE (0x1 << 0)
714 #define RT5682S_PWR_LDO_PLLA (0x1 << 15)
716 #define RT5682S_PWR_LDO_PLLB (0x1 << 14)
718 #define RT5682S_PWR_BIAS_PLLA (0x1 << 13)
720 #define RT5682S_PWR_BIAS_PLLB (0x1 << 12)
722 #define RT5682S_PWR_CBJ (0x1 << 9)
724 #define RT5682S_RSTB_PLLB (0x1 << 7)
726 #define RT5682S_RSTB_PLLA (0x1 << 6)
728 #define RT5682S_PWR_PLLB (0x1 << 5)
730 #define RT5682S_PWR_PLLA (0x1 << 4)
731 #define RT5682S_PWR_PLLA_BIT 4
732 #define RT5682S_PWR_LDO_MB2 (0x1 << 2)
734 #define RT5682S_PWR_LDO_MB1 (0x1 << 1)
736 #define RT5682S_PWR_BGLDO (0x1 << 0)
740 #define RT5682S_PWR_CLK_COMP_8FS (0x1 << 15)
750 #define RT5682S_PWR_STO1_DAC_L (0x1 << 5)
752 #define RT5682S_PWR_STO1_DAC_R (0x1 << 4)
753 #define RT5682S_PWR_STO1_DAC_R_BIT 4
759 #define RT5682S_SYS_CLK_DET (0x1 << 15)
761 #define RT5682S_PLL1_CLK_DET (0x1 << 14)
765 #define RT5682S_DMIC_1_EN_MASK (0x1 << 15)
768 #define RT5682S_DMIC_1_EN (0x1 << 15)
770 #define RT5682S_FIFO_CLK_DIV_2 (0x1 << 12)
771 #define RT5682S_DMIC_1_DP_MASK (0x3 << 4)
772 #define RT5682S_DMIC_1_DP_SFT 4
773 #define RT5682S_DMIC_1_DP_GPIO2 (0x0 << 4)
774 #define RT5682S_DMIC_1_DP_GPIO5 (0x1 << 4)
779 #define RT5682S_SEL_ADCDAT_MASK (0x1 << 15)
781 #define RT5682S_SEL_ADCDAT_IN (0x1 << 15)
786 #define RT5682S_I2S1_TX_CHL_20 (0x1 << 12)
793 #define RT5682S_I2S1_RX_CHL_20 (0x1 << 8)
797 #define RT5682S_I2S1_MONO_MASK (0x1 << 7)
798 #define RT5682S_I2S1_MONO_EN (0x1 << 7)
800 #define RT5682S_I2S1_DL_MASK (0x7 << 4)
801 #define RT5682S_I2S1_DL_SFT 4
802 #define RT5682S_I2S1_DL_16 (0x0 << 4)
803 #define RT5682S_I2S1_DL_20 (0x1 << 4)
804 #define RT5682S_I2S1_DL_24 (0x2 << 4)
805 #define RT5682S_I2S1_DL_32 (0x3 << 4)
806 #define RT5682S_I2S1_DL_8 (0x4 << 4)
809 #define RT5682S_I2S2_MS_MASK (0x1 << 15)
812 #define RT5682S_I2S2_MS_S (0x1 << 15)
813 #define RT5682S_I2S2_PIN_CFG_MASK (0x1 << 14)
815 #define RT5682S_I2S2_OUT_MASK (0x1 << 9)
818 #define RT5682S_I2S2_OUT_M (0x1 << 9)
819 #define RT5682S_I2S_BP_MASK (0x1 << 8)
822 #define RT5682S_I2S_BP_INV (0x1 << 8)
823 #define RT5682S_I2S2_MONO_MASK (0x1 << 7)
824 #define RT5682S_I2S2_MONO_EN (0x1 << 7)
826 #define RT5682S_I2S2_DL_MASK (0x7 << 4)
827 #define RT5682S_I2S2_DL_SFT 4
828 #define RT5682S_I2S2_DL_8 (0x0 << 4)
829 #define RT5682S_I2S2_DL_16 (0x1 << 4)
830 #define RT5682S_I2S2_DL_20 (0x2 << 4)
831 #define RT5682S_I2S2_DL_24 (0x3 << 4)
832 #define RT5682S_I2S2_DL_32 (0x4 << 4)
836 #define RT5682S_I2S_DF_LEFT (0x1)
846 #define RT5682S_ADC_OSR_D_2 (0x1 << 12)
858 #define RT5682S_I2S_M_D_2 (0x1 << 8)
868 #define RT5682S_I2S_M_CLK_SRC_MASK (0x7 << 4)
869 #define RT5682S_I2S_M_CLK_SRC_SFT 4
873 #define RT5682S_DAC_OSR_D_2 (0x1 << 0)
884 #define RT5682S_I2S2_BCLK_MS2_MASK (0x1 << 11)
887 #define RT5682S_I2S2_BCLK_MS2_64 (0x1 << 11)
893 #define RT5682S_TDM_TX_CH_4 (0x1 << 12)
898 #define RT5682S_TDM_RX_CH_4 (0x1 << 8)
901 #define RT5682S_TDM_ADC_LCA_MASK (0x7 << 4)
902 #define RT5682S_TDM_ADC_LCA_SFT 4
914 #define RT5682S_TDM_EN (0x1 << 7)
917 #define RT5682S_TDM_S_BP_MASK (0x1 << 15)
920 #define RT5682S_TDM_S_BP_INV (0x1 << 15)
921 #define RT5682S_TDM_S_LP_MASK (0x1 << 14)
924 #define RT5682S_TDM_S_LP_INV (0x1 << 14)
928 #define RT5682S_TDM_DF_LEFT (0x1 << 11)
936 #define RT5682S_TDM_BCLK_MS1_64 (0x1 << 8)
940 #define RT5682S_TDM_CL_MASK (0x3 << 4)
941 #define RT5682S_TDM_CL_16 (0x0 << 4)
942 #define RT5682S_TDM_CL_20 (0x1 << 4)
943 #define RT5682S_TDM_CL_24 (0x2 << 4)
944 #define RT5682S_TDM_CL_32 (0x3 << 4)
945 #define RT5682S_TDM_M_BP_MASK (0x1 << 2)
948 #define RT5682S_TDM_M_BP_INV (0x1 << 2)
949 #define RT5682S_TDM_M_LP_MASK (0x1 << 1)
952 #define RT5682S_TDM_M_LP_INV (0x1 << 1)
953 #define RT5682S_TDM_MS_MASK (0x1 << 0)
956 #define RT5682S_TDM_MS_M (0x1 << 0)
964 #define RT5682S_PLL_SRC_BCLK1 (0x1 << 8)
968 #define RT5682S_DA_ASRC_MASK (0x1 << 13)
970 #define RT5682S_DAC_STO1_ASRC_MASK (0x1 << 12)
972 #define RT5682S_AD_ASRC_MASK (0x1 << 8)
974 #define RT5682S_AD_ASRC_SEL_MASK (0x1 << 4)
975 #define RT5682S_AD_ASRC_SEL_SFT 4
976 #define RT5682S_DMIC_ASRC_MASK (0x1 << 3)
978 #define RT5682S_ADC_STO1_ASRC_MASK (0x1 << 2)
980 #define RT5682S_DA_ASRC_SEL_MASK (0x1 << 0)
989 /* ASRC Control 4 (0x0086) */
996 #define RT5682S_ASRCIN_FTK_M2_MASK (0x7 << 4)
997 #define RT5682S_ASRCIN_FTK_M2_SFT 4
1000 #define RT5682S_ASRCIN_AUTO_CLKOUT_MASK (0x1 << 5)
1001 #define RT5682S_ASRCIN_AUTO_CLKOUT_EN (0x1 << 5)
1003 #define RT5682S_ASRCIN_AUTO_RST_MASK (0x1 << 4)
1004 #define RT5682S_ASRCIN_AUTO_RST_EN (0x1 << 4)
1005 #define RT5682S_ASRCIN_AUTO_RST_DIS (0x0 << 4)
1009 #define RT5682S_SEL_LRCK_DET_DIV2 (0x1)
1013 #define RT5682S_OUT_HP_L_EN (0x1 << 6)
1014 #define RT5682S_OUT_HP_R_EN (0x1 << 5)
1015 #define RT5682S_LDO_PUMP_EN (0x1 << 4)
1016 #define RT5682S_LDO_PUMP_EN_SFT 4
1017 #define RT5682S_PUMP_EN (0x1 << 3)
1019 #define RT5682S_CAPLESS_L_EN (0x1 << 1)
1021 #define RT5682S_CAPLESS_R_EN (0x1 << 0)
1025 #define RT5682S_RAMP_MASK (0x1 << 12)
1028 #define RT5682S_RAMP_EN (0x1 << 12)
1029 #define RT5682S_BPS_MASK (0x1 << 11)
1032 #define RT5682S_BPS_EN (0x1 << 11)
1033 #define RT5682S_FAST_UPDN_MASK (0x1 << 10)
1036 #define RT5682S_FAST_UPDN_EN (0x1 << 10)
1037 #define RT5682S_VLO_MASK (0x1 << 7)
1040 #define RT5682S_VLO_33V (0x1 << 7)
1043 #define RT5682S_OSW_L_MASK (0x1 << 11)
1046 #define RT5682S_OSW_L_EN (0x1 << 11)
1047 #define RT5682S_OSW_R_MASK (0x1 << 10)
1050 #define RT5682S_OSW_R_EN (0x1 << 10)
1054 #define RT5682S_PM_HP_MV (0x1 << 8)
1061 #define RT5682S_MIC1_OV_2V4 (0x1 << 14)
1067 #define RT5682S_MIC2_OV_2V4 (0x1 << 8)
1072 #define RT5682S_PWR_CLK25M_MASK (0x1 << 9)
1075 #define RT5682S_PWR_CLK25M_PU (0x1 << 9)
1076 #define RT5682S_PWR_CLK1M_MASK (0x1 << 8)
1079 #define RT5682S_PWR_CLK1M_PU (0x1 << 8)
1092 /* PLL M/N/K Code Control 4 (0x009b) */
1098 #define RT5682S_PLLB_SEL_PS_MASK (0x1 << 13)
1100 #define RT5682S_PLLB_BYP_PS_MASK (0x1 << 12)
1102 #define RT5682S_PLLB_M_BP_MASK (0x1 << 11)
1104 #define RT5682S_PLLB_K_BP_MASK (0x1 << 10)
1106 #define RT5682S_PLLA_M_BP_MASK (0x1 << 7)
1108 #define RT5682S_PLLA_K_BP_MASK (0x1 << 6)
1112 #define RT5682S_PLLB_SRC_MASK (0x1)
1113 #define RT5682S_PLLB_SRC_DFIN (0x1)
1117 #define RT5682S_POW_IRQ (0x1 << 15)
1118 #define RT5682S_POW_JDH (0x1 << 14)
1121 #define RT5682S_I2S2_M_CLK_SRC_MASK (0x7 << 4)
1122 #define RT5682S_I2S2_M_CLK_SRC_SFT 4
1125 #define RT5682S_I2S2_M_D_2 (0x1)
1138 #define RT5682S_JD1_PULSE_EN_MASK (0x1 << 10)
1141 #define RT5682S_JD1_PULSE_EN (0x1 << 10)
1144 #define RT5682S_JD1_EN_MASK (0x1 << 15)
1147 #define RT5682S_JD1_EN (0x1 << 15)
1148 #define RT5682S_JD1_POL_MASK (0x1 << 13)
1150 #define RT5682S_JD1_POL_INV (0x1 << 13)
1151 #define RT5682S_JD1_IRQ_MASK (0x1 << 10)
1153 #define RT5682S_JD1_IRQ_PUL (0x1 << 10)
1156 #define RT5682S_IL_IRQ_MASK (0x1 << 7)
1158 #define RT5682S_IL_IRQ_EN (0x1 << 7)
1159 #define RT5682S_IL_IRQ_TYPE_MASK (0x1 << 4)
1160 #define RT5682S_IL_IRQ_LEV (0x0 << 4)
1161 #define RT5682S_IL_IRQ_PUL (0x1 << 4)
1167 #define RT5682S_GP1_PIN_IRQ (0x1 << 14)
1172 #define RT5682S_GP2_PIN_LRCK2 (0x1 << 12)
1177 #define RT5682S_GP3_PIN_BCLK2 (0x1 << 10)
1182 #define RT5682S_GP4_PIN_ADCDAT1 (0x1 << 8)
1188 #define RT5682S_GP5_PIN_DACDAT1 (0x1 << 6)
1190 #define RT5682S_GP6_PIN_MASK (0x1 << 5)
1193 #define RT5682S_GP6_PIN_LRCK1 (0x1 << 5)
1196 #define RT5682S_GP1_PF_MASK (0x1 << 15)
1198 #define RT5682S_GP1_PF_OUT (0x1 << 15)
1199 #define RT5682S_GP1_OUT_MASK (0x1 << 14)
1201 #define RT5682S_GP1_OUT_H (0x1 << 14)
1202 #define RT5682S_GP2_PF_MASK (0x1 << 13)
1204 #define RT5682S_GP2_PF_OUT (0x1 << 13)
1205 #define RT5682S_GP2_OUT_MASK (0x1 << 12)
1207 #define RT5682S_GP2_OUT_H (0x1 << 12)
1208 #define RT5682S_GP3_PF_MASK (0x1 << 11)
1210 #define RT5682S_GP3_PF_OUT (0x1 << 11)
1211 #define RT5682S_GP3_OUT_MASK (0x1 << 10)
1213 #define RT5682S_GP3_OUT_H (0x1 << 10)
1214 #define RT5682S_GP4_PF_MASK (0x1 << 9)
1216 #define RT5682S_GP4_PF_OUT (0x1 << 9)
1217 #define RT5682S_GP4_OUT_MASK (0x1 << 8)
1219 #define RT5682S_GP4_OUT_H (0x1 << 8)
1220 #define RT5682S_GP5_PF_MASK (0x1 << 7)
1222 #define RT5682S_GP5_PF_OUT (0x1 << 7)
1223 #define RT5682S_GP5_OUT_MASK (0x1 << 6)
1225 #define RT5682S_GP5_OUT_H (0x1 << 6)
1226 #define RT5682S_GP6_PF_MASK (0x1 << 5)
1228 #define RT5682S_GP6_PF_OUT (0x1 << 5)
1229 #define RT5682S_GP6_OUT_MASK (0x1 << 4)
1230 #define RT5682S_GP6_OUT_L (0x0 << 4)
1231 #define RT5682S_GP6_OUT_H (0x1 << 4)
1234 #define RT5682S_GP6_ST (0x1 << 6)
1235 #define RT5682S_GP5_ST (0x1 << 5)
1236 #define RT5682S_GP4_ST (0x1 << 4)
1237 #define RT5682S_GP3_ST (0x1 << 3)
1238 #define RT5682S_GP2_ST (0x1 << 2)
1239 #define RT5682S_GP1_ST (0x1 << 1)
1242 #define RT5682S_ZCD_MASK (0x1 << 10)
1245 #define RT5682S_ZCD_PU (0x1 << 10)
1247 /* 4 Button Inline Command Control 2 (0x00e3) */
1248 #define RT5682S_4BTN_IL_MASK (0x1 << 15)
1249 #define RT5682S_4BTN_IL_EN (0x1 << 15)
1251 #define RT5682S_4BTN_IL_RST_MASK (0x1 << 14)
1252 #define RT5682S_4BTN_IL_NOR (0x1 << 14)
1255 /* 4 Button Inline Command Control 3~6 (0x00e5~0x00e8) */
1262 #define RT5682S_JDH_RS_MASK (0x1 << 4)
1263 #define RT5682S_JDH_NO_PLUG (0x1 << 4)
1264 #define RT5682S_JDH_PLUG (0x0 << 4)
1267 #define RT5682S_LDO_DACREF_MASK (0x3 << 4)
1268 #define RT5682S_LDO_DACREF_1_607V (0x0 << 4)
1269 #define RT5682S_LDO_DACREF_1_5V (0x1 << 4)
1270 #define RT5682S_LDO_DACREF_1_406V (0x2 << 4)
1271 #define RT5682S_LDO_DACREF_1_731V (0x3 << 4)
1274 #define RT5682S_CP_CLK_HP_MASK (0x3 << 4)
1275 #define RT5682S_CP_CLK_HP_100KHZ (0x0 << 4)
1276 #define RT5682S_CP_CLK_HP_200KHZ (0x1 << 4)
1277 #define RT5682S_CP_CLK_HP_300KHZ (0x2 << 4)
1278 #define RT5682S_CP_CLK_HP_600KHZ (0x3 << 4)
1281 #define RT5682S_PAD_DRV_GP1_MASK (0x1 << 14)
1282 #define RT5682S_PAD_DRV_GP1_HIGH (0x1 << 14)
1284 #define RT5682S_PAD_DRV_GP2_MASK (0x1 << 12)
1285 #define RT5682S_PAD_DRV_GP2_HIGH (0x1 << 12)
1287 #define RT5682S_PAD_DRV_GP3_MASK (0x1 << 10)
1288 #define RT5682S_PAD_DRV_GP3_HIGH (0x1 << 10)
1290 #define RT5682S_PAD_DRV_GP4_MASK (0x1 << 8)
1291 #define RT5682S_PAD_DRV_GP4_HIGH (0x1 << 8)
1293 #define RT5682S_PAD_DRV_GP5_MASK (0x1 << 6)
1294 #define RT5682S_PAD_DRV_GP5_HIGH (0x1 << 6)
1296 #define RT5682S_PAD_DRV_GP6_MASK (0x1 << 4)
1297 #define RT5682S_PAD_DRV_GP6_HIGH (0x1 << 4)
1298 #define RT5682S_PAD_DRV_GP6_LOW (0x0 << 4)
1301 #define RT5682S_CKXEN_DAC1_MASK (0x1 << 13)
1303 #define RT5682S_CKGEN_DAC1_MASK (0x1 << 12)
1307 #define RT5682S_CKXEN_ADC1_MASK (0x1 << 13)
1309 #define RT5682S_CKGEN_ADC1_MASK (0x1 << 12)
1313 #define RT5682S_SEL_CLK_VOL_MASK (0x1 << 15)
1314 #define RT5682S_SEL_CLK_VOL_EN (0x1 << 15)
1318 #define RT5682S_AD2DA_LB_MASK (0x1 << 10)
1322 #define RT5682S_NG2_EN_MASK (0x1 << 15)
1323 #define RT5682S_NG2_EN (0x1 << 15)
1327 #define RT5682S_DEB_STO_DAC_MASK (0x7 << 4)
1328 #define RT5682S_DEB_80_MS (0x0 << 4)
1334 #define RT5682S_HP_SIG_SRC_IMPE_REG (0x1)
1338 #define RT5682S_SAR_BUTDET_MASK (0x1 << 15)
1339 #define RT5682S_SAR_BUTDET_EN (0x1 << 15)
1341 #define RT5682S_SAR_BUTDET_POW_MASK (0x1 << 14)
1342 #define RT5682S_SAR_BUTDET_POW_SAV (0x1 << 14)
1344 #define RT5682S_SAR_BUTDET_RST_MASK (0x1 << 13)
1345 #define RT5682S_SAR_BUTDET_RST_NORM (0x1 << 13)
1347 #define RT5682S_SAR_POW_MASK (0x1 << 12)
1348 #define RT5682S_SAR_POW_EN (0x1 << 12)
1350 #define RT5682S_SAR_RST_MASK (0x1 << 11)
1351 #define RT5682S_SAR_RST_NORMAL (0x1 << 11)
1353 #define RT5682S_SAR_BYPASS_MASK (0x1 << 10)
1354 #define RT5682S_SAR_BYPASS_EN (0x1 << 10)
1358 #define RT5682S_SAR_SEL_MODE_MASK (0x1 << 7)
1359 #define RT5682S_SAR_SEL_MODE_CMP (0x1 << 7)
1361 #define RT5682S_SAR_SEL_MB1_2_CTL_MASK (0x1 << 5)
1362 #define RT5682S_SAR_SEL_MB1_2_AUTO (0x1 << 5)
1364 #define RT5682S_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1365 #define RT5682S_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1366 #define RT5682S_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1369 #define RT5682S_SAR_ADC_PSV_MASK (0x1 << 4)
1370 #define RT5682S_SAR_ADC_PSV_ENTRY (0x1 << 4)
1379 #define RT5682S_CP_SW_SIZE_MASK (0x7 << 4)
1380 #define RT5682S_CP_SW_SIZE_L (0x4 << 4)
1381 #define RT5682S_CP_SW_SIZE_M (0x2 << 4)
1382 #define RT5682S_CP_SW_SIZE_S (0x1 << 4)
1418 RT5682S_DA_STEREO1_FILTER = 0x1,
1419 RT5682S_AD_STEREO1_FILTER = (0x1 << 1),