Lines Matching +full:4 +full:x1
359 #define RT5668_L_MUTE (0x1 << 15)
361 #define RT5668_VOL_L_MUTE (0x1 << 14)
363 #define RT5668_R_MUTE (0x1 << 7)
365 #define RT5668_VOL_R_MUTE (0x1 << 6)
383 #define RT5668_EMB_JD_EN (0x1 << 15)
385 #define RT5668_EMB_JD_RST (0x1 << 14)
386 #define RT5668_JD_MODE (0x1 << 13)
388 #define RT5668_DET_TYPE (0x1 << 12)
390 #define RT5668_POLA_EXT_JD_MASK (0x1 << 11)
391 #define RT5668_POLA_EXT_JD_LOW (0x1 << 11)
393 #define RT5668_EXT_JD_DIG (0x1 << 9)
394 #define RT5668_POL_FAST_OFF_MASK (0x1 << 8)
395 #define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)
397 #define RT5668_FAST_OFF_MASK (0x1 << 7)
398 #define RT5668_FAST_OFF_EN (0x1 << 7)
400 #define RT5668_VREF_POW_MASK (0x1 << 6)
402 #define RT5668_VREF_POW_REG (0x1 << 6)
403 #define RT5668_MB1_PATH_MASK (0x1 << 5)
404 #define RT5668_CTRL_MB1_REG (0x1 << 5)
406 #define RT5668_MB2_PATH_MASK (0x1 << 4)
407 #define RT5668_CTRL_MB2_REG (0x1 << 4)
408 #define RT5668_CTRL_MB2_FSM (0x0 << 4)
409 #define RT5668_TRIG_JD_MASK (0x1 << 3)
410 #define RT5668_TRIG_JD_HIGH (0x1 << 3)
412 #define RT5668_MIC_CAP_MASK (0x1 << 1)
413 #define RT5668_MIC_CAP_HS (0x1 << 1)
415 #define RT5668_MIC_CAP_SRC_MASK (0x1)
416 #define RT5668_MIC_CAP_SRC_REG (0x1)
420 #define RT5668_EXT_JD_SRC (0x7 << 4)
421 #define RT5668_EXT_JD_SRC_SFT 4
422 #define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
423 #define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
424 #define RT5668_EXT_JD_SRC_JDH (0x2 << 4)
425 #define RT5668_EXT_JD_SRC_JDL (0x3 << 4)
426 #define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4)
430 #define RT5668_CBJ_IN_BUF_EN (0x1 << 7)
432 /* Combo Jack and Type Detection Control 4 (0x0013) */
435 #define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12)
436 #define RT5668_CBJ_JD_TEST_MASK (0x1 << 6)
438 #define RT5668_CBJ_JD_TEST_MODE (0x1 << 6)
459 #define RT5668_ST_SRC_SEL (0x1 << 8)
461 #define RT5668_ST_EN_MASK (0x1 << 6)
463 #define RT5668_ST_EN (0x1 << 6)
467 #define RT5668_M_STO1_ADC_L1 (0x1 << 15)
469 #define RT5668_M_STO1_ADC_L2 (0x1 << 14)
471 #define RT5668_STO1_ADC1L_SRC_MASK (0x1 << 13)
473 #define RT5668_STO1_ADC1_SRC_ADC (0x1 << 13)
475 #define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12)
479 #define RT5668_STO1_DD_L_SRC_MASK (0x1 << 9)
481 #define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8)
483 #define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
485 #define RT5668_M_STO1_ADC_R1 (0x1 << 7)
487 #define RT5668_M_STO1_ADC_R2 (0x1 << 6)
489 #define RT5668_STO1_ADC1R_SRC_MASK (0x1 << 5)
491 #define RT5668_STO1_ADC2R_SRC_MASK (0x1 << 4)
492 #define RT5668_STO1_ADC2R_SRC_SFT 4
497 #define RT5668_M_ADCMIX_L (0x1 << 15)
499 #define RT5668_M_DAC1_L (0x1 << 14)
501 #define RT5668_DAC1_R_SEL_MASK (0x1 << 10)
503 #define RT5668_DAC1_L_SEL_MASK (0x1 << 8)
505 #define RT5668_M_ADCMIX_R (0x1 << 7)
507 #define RT5668_M_DAC1_R (0x1 << 6)
511 #define RT5668_M_DAC_L1_STO_L (0x1 << 15)
513 #define RT5668_G_DAC_L1_STO_L_MASK (0x1 << 14)
515 #define RT5668_M_DAC_R1_STO_L (0x1 << 13)
517 #define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12)
519 #define RT5668_M_DAC_L1_STO_R (0x1 << 7)
521 #define RT5668_G_DAC_L1_STO_R_MASK (0x1 << 6)
523 #define RT5668_M_DAC_R1_STO_R (0x1 << 5)
525 #define RT5668_G_DAC_R1_STO_R_MASK (0x1 << 4)
526 #define RT5668_G_DAC_R1_STO_R_SFT 4
529 #define RT5668_M_ST_STO_L (0x1 << 9)
531 #define RT5668_M_ST_STO_R (0x1 << 8)
533 #define RT5668_DAC_L1_SRC_MASK (0x3 << 4)
534 #define RT5668_A_DACL1_SFT 4
545 #define RT5668_M_CBJ_RM1_L (0x1 << 7)
549 #define RT5668_PWR_I2S1 (0x1 << 15)
551 #define RT5668_PWR_I2S2 (0x1 << 14)
553 #define RT5668_PWR_DAC_L1 (0x1 << 11)
555 #define RT5668_PWR_DAC_R1 (0x1 << 10)
557 #define RT5668_PWR_LDO (0x1 << 8)
559 #define RT5668_PWR_ADC_L1 (0x1 << 4)
560 #define RT5668_PWR_ADC_L1_BIT 4
561 #define RT5668_PWR_ADC_R1 (0x1 << 3)
563 #define RT5668_DIG_GATE_CTRL (0x1 << 0)
568 #define RT5668_PWR_ADC_S1F (0x1 << 15)
570 #define RT5668_PWR_DAC_S1F (0x1 << 10)
574 #define RT5668_PWR_VREF1 (0x1 << 15)
576 #define RT5668_PWR_FV1 (0x1 << 14)
578 #define RT5668_PWR_VREF2 (0x1 << 13)
580 #define RT5668_PWR_FV2 (0x1 << 12)
583 #define RT5668_PWR_MB (0x1 << 9)
585 #define RT5668_PWR_BG (0x1 << 7)
587 #define RT5668_LDO1_BYPASS_MASK (0x1 << 6)
588 #define RT5668_LDO1_BYPASS (0x1 << 6)
591 #define RT5668_LDO1_DVO_MASK (0x3 << 4)
592 #define RT5668_LDO1_DVO_09 (0x0 << 4)
593 #define RT5668_LDO1_DVO_10 (0x1 << 4)
594 #define RT5668_LDO1_DVO_12 (0x2 << 4)
595 #define RT5668_LDO1_DVO_14 (0x3 << 4)
598 #define RT5668_HP_DRIVER_3X (0x1 << 2)
600 #define RT5668_PWR_HA_L (0x1 << 1)
602 #define RT5668_PWR_HA_R (0x1 << 0)
606 #define RT5668_PWR_MB1 (0x1 << 11)
609 #define RT5668_PWR_MB2 (0x1 << 10)
612 #define RT5668_PWR_JDH (0x1 << 3)
614 #define RT5668_PWR_JDL (0x1 << 2)
616 #define RT5668_PWR_RM1_L (0x1 << 1)
620 #define RT5668_PWR_CBJ (0x1 << 9)
622 #define RT5668_PWR_PLL (0x1 << 6)
624 #define RT5668_PWR_PLL2B (0x1 << 5)
626 #define RT5668_PWR_PLL2F (0x1 << 4)
627 #define RT5668_PWR_PLL2F_BIT 4
628 #define RT5668_PWR_LDO2 (0x1 << 2)
630 #define RT5668_PWR_DET_SPKVDD (0x1 << 1)
634 #define RT5668_PWR_STO1_DAC_L (0x1 << 5)
636 #define RT5668_PWR_STO1_DAC_R (0x1 << 4)
637 #define RT5668_PWR_STO1_DAC_R_BIT 4
640 #define RT5668_SYS_CLK_DET (0x1 << 15)
642 #define RT5668_PLL1_CLK_DET (0x1 << 14)
644 #define RT5668_PLL2_CLK_DET (0x1 << 13)
650 #define RT5668_DMIC_1_EN_MASK (0x1 << 15)
653 #define RT5668_DMIC_1_EN (0x1 << 15)
654 #define RT5668_DMIC_1_DP_MASK (0x3 << 4)
655 #define RT5668_DMIC_1_DP_SFT 4
656 #define RT5668_DMIC_1_DP_GPIO2 (0x0 << 4)
657 #define RT5668_DMIC_1_DP_GPIO5 (0x1 << 4)
662 #define RT5668_SEL_ADCDAT_MASK (0x1 << 15)
664 #define RT5668_SEL_ADCDAT_IN (0x1 << 15)
669 #define RT5668_I2S1_TX_CHL_20 (0x1 << 12)
676 #define RT5668_I2S1_RX_CHL_20 (0x1 << 8)
680 #define RT5668_I2S1_MONO_MASK (0x1 << 7)
681 #define RT5668_I2S1_MONO_EN (0x1 << 7)
683 #define RT5668_I2S2_MONO_MASK (0x1 << 6)
684 #define RT5668_I2S2_MONO_EN (0x1 << 6)
686 #define RT5668_I2S1_DL_MASK (0x7 << 4)
687 #define RT5668_I2S1_DL_SFT 4
688 #define RT5668_I2S1_DL_16 (0x0 << 4)
689 #define RT5668_I2S1_DL_20 (0x1 << 4)
690 #define RT5668_I2S1_DL_24 (0x2 << 4)
691 #define RT5668_I2S1_DL_32 (0x3 << 4)
692 #define RT5668_I2S1_DL_8 (0x4 << 4)
695 #define RT5668_I2S2_MS_MASK (0x1 << 15)
698 #define RT5668_I2S2_MS_S (0x1 << 15)
699 #define RT5668_I2S2_PIN_CFG_MASK (0x1 << 14)
701 #define RT5668_I2S2_CLK_SEL_MASK (0x1 << 11)
703 #define RT5668_I2S2_OUT_MASK (0x1 << 9)
706 #define RT5668_I2S2_OUT_M (0x1 << 9)
707 #define RT5668_I2S_BP_MASK (0x1 << 8)
710 #define RT5668_I2S_BP_INV (0x1 << 8)
711 #define RT5668_I2S2_MONO_EN (0x1 << 6)
713 #define RT5668_I2S2_DL_MASK (0x3 << 4)
714 #define RT5668_I2S2_DL_SFT 4
715 #define RT5668_I2S2_DL_16 (0x0 << 4)
716 #define RT5668_I2S2_DL_20 (0x1 << 4)
717 #define RT5668_I2S2_DL_24 (0x2 << 4)
718 #define RT5668_I2S2_DL_8 (0x3 << 4)
722 #define RT5668_I2S_DF_LEFT (0x1)
732 #define RT5668_ADC_OSR_D_2 (0x1 << 12)
744 #define RT5668_I2S_M_D_2 (0x1 << 8)
754 #define RT5668_I2S_CLK_SRC_MASK (0x7 << 4)
755 #define RT5668_I2S_CLK_SRC_SFT 4
756 #define RT5668_I2S_CLK_SRC_MCLK (0x0 << 4)
757 #define RT5668_I2S_CLK_SRC_PLL1 (0x1 << 4)
758 #define RT5668_I2S_CLK_SRC_PLL2 (0x2 << 4)
759 #define RT5668_I2S_CLK_SRC_SDW (0x3 << 4)
760 #define RT5668_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */
764 #define RT5668_DAC_OSR_D_2 (0x1 << 0)
775 #define RT5668_I2S2_BCLK_MS2_MASK (0x1 << 11)
778 #define RT5668_I2S2_BCLK_MS2_64 (0x1 << 11)
784 #define RT5668_TDM_TX_CH_4 (0x1 << 12)
789 #define RT5668_TDM_RX_CH_4 (0x1 << 8)
792 #define RT5668_TDM_ADC_LCA_MASK (0xf << 4)
793 #define RT5668_TDM_ADC_LCA_SFT 4
801 #define RT5668_TDM_ADC_SEL_SFT 4
804 #define RT5668_TDM_S_BP_MASK (0x1 << 15)
807 #define RT5668_TDM_S_BP_INV (0x1 << 15)
808 #define RT5668_TDM_S_LP_MASK (0x1 << 14)
811 #define RT5668_TDM_S_LP_INV (0x1 << 14)
815 #define RT5668_TDM_DF_LEFT (0x1 << 11)
820 #define RT5668_TDM_CL_MASK (0x3 << 4)
821 #define RT5668_TDM_CL_16 (0x0 << 4)
822 #define RT5668_TDM_CL_20 (0x1 << 4)
823 #define RT5668_TDM_CL_24 (0x2 << 4)
824 #define RT5668_TDM_CL_32 (0x3 << 4)
825 #define RT5668_TDM_M_BP_MASK (0x1 << 2)
828 #define RT5668_TDM_M_BP_INV (0x1 << 2)
829 #define RT5668_TDM_M_LP_MASK (0x1 << 1)
832 #define RT5668_TDM_M_LP_INV (0x1 << 1)
833 #define RT5668_TDM_MS_MASK (0x1 << 0)
836 #define RT5668_TDM_MS_S (0x1 << 0)
842 #define RT5668_SCLK_SRC_PLL1 (0x1 << 13)
849 #define RT5668_PLL1_SRC_BCLK1 (0x1 << 10)
855 #define RT5668_PLL2_SRC_BCLK1 (0x1 << 8)
875 #define RT5668_PLL_M_BP (0x1 << 11)
877 #define RT5668_PLL_K_BP (0x1 << 10)
881 #define RT5668_DA_ASRC_MASK (0x1 << 13)
883 #define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
885 #define RT5668_AD_ASRC_MASK (0x1 << 8)
887 #define RT5668_AD_ASRC_SEL_MASK (0x1 << 4)
888 #define RT5668_AD_ASRC_SEL_SFT 4
889 #define RT5668_DMIC_ASRC_MASK (0x1 << 3)
891 #define RT5668_ADC_STO1_ASRC_MASK (0x1 << 2)
893 #define RT5668_DA_ASRC_SEL_MASK (0x1 << 0)
900 /* ASRC Control 4 (0x0086) */
907 #define RT5668_ASRCIN_FTK_M2_MASK (0x7 << 4)
908 #define RT5668_ASRCIN_FTK_M2_SFT 4
911 #define RT5668_PLL2_OUT_MASK (0x1 << 8)
913 #define RT5668_PLL2_OUT_49M (0x1 << 8)
914 #define RT5668_SDW_REF_2_MASK (0xf << 4)
915 #define RT5668_SDW_REF_2_SFT 4
916 #define RT5668_SDW_REF_2_48K (0x0 << 4)
917 #define RT5668_SDW_REF_2_96K (0x1 << 4)
918 #define RT5668_SDW_REF_2_192K (0x2 << 4)
919 #define RT5668_SDW_REF_2_32K (0x3 << 4)
920 #define RT5668_SDW_REF_2_24K (0x4 << 4)
921 #define RT5668_SDW_REF_2_16K (0x5 << 4)
922 #define RT5668_SDW_REF_2_12K (0x6 << 4)
923 #define RT5668_SDW_REF_2_8K (0x7 << 4)
924 #define RT5668_SDW_REF_2_44K (0x8 << 4)
925 #define RT5668_SDW_REF_2_88K (0x9 << 4)
926 #define RT5668_SDW_REF_2_176K (0xa << 4)
927 #define RT5668_SDW_REF_2_353K (0xb << 4)
928 #define RT5668_SDW_REF_2_22K (0xc << 4)
929 #define RT5668_SDW_REF_2_384K (0xd << 4)
930 #define RT5668_SDW_REF_2_11K (0xe << 4)
934 #define RT5668_SDW_REF_1_96K (0x1 << 0)
950 #define RT5668_PUMP_EN (0x1 << 3)
952 #define RT5668_CAPLESS_EN (0x1 << 0)
956 #define RT5668_RAMP_MASK (0x1 << 12)
959 #define RT5668_RAMP_EN (0x1 << 12)
960 #define RT5668_BPS_MASK (0x1 << 11)
963 #define RT5668_BPS_EN (0x1 << 11)
964 #define RT5668_FAST_UPDN_MASK (0x1 << 10)
967 #define RT5668_FAST_UPDN_EN (0x1 << 10)
968 #define RT5668_VLO_MASK (0x1 << 7)
971 #define RT5668_VLO_33V (0x1 << 7)
974 #define RT5668_OSW_L_MASK (0x1 << 11)
977 #define RT5668_OSW_L_EN (0x1 << 11)
978 #define RT5668_OSW_R_MASK (0x1 << 10)
981 #define RT5668_OSW_R_EN (0x1 << 10)
985 #define RT5668_PM_HP_MV (0x1 << 8)
990 #define RT5668_IB_HP_25IL (0x1 << 6)
998 #define RT5668_MIC1_OV_2V4 (0x1 << 14)
1001 #define RT5668_MIC1_CLK_MASK (0x1 << 13)
1004 #define RT5668_MIC1_CLK_EN (0x1 << 13)
1005 #define RT5668_MIC1_OVCD_MASK (0x1 << 12)
1008 #define RT5668_MIC1_OVCD_EN (0x1 << 12)
1012 #define RT5668_MIC1_OVTH_960UA (0x1 << 10)
1018 #define RT5668_MIC2_OV_2V4 (0x1 << 8)
1021 #define RT5668_MIC2_CLK_MASK (0x1 << 7)
1024 #define RT5668_MIC2_CLK_EN (0x1 << 7)
1025 #define RT5668_MIC2_OVTH_MASK (0x3 << 4)
1026 #define RT5668_MIC2_OVTH_SFT 4
1027 #define RT5668_MIC2_OVTH_768UA (0x0 << 4)
1028 #define RT5668_MIC2_OVTH_960UA (0x1 << 4)
1029 #define RT5668_MIC2_OVTH_1152UA (0x2 << 4)
1030 #define RT5668_MIC2_OVTH_1960UA (0x3 << 4)
1031 #define RT5668_PWR_MB_MASK (0x1 << 3)
1034 #define RT5668_PWR_MB_PU (0x1 << 3)
1037 #define RT5668_PWR_CLK25M_MASK (0x1 << 9)
1040 #define RT5668_PWR_CLK25M_PU (0x1 << 9)
1041 #define RT5668_PWR_CLK1M_MASK (0x1 << 8)
1044 #define RT5668_PWR_CLK1M_PU (0x1 << 8)
1047 #define RT5668_POW_IRQ (0x1 << 15)
1048 #define RT5668_POW_JDH (0x1 << 14)
1049 #define RT5668_POW_JDL (0x1 << 13)
1050 #define RT5668_POW_ANA (0x1 << 12)
1054 #define RT5668_CLK_SRC_PLL1 (0x1)
1059 #define RT5668_I2S_PD_2 (0x1)
1069 #define RT5668_I2S2_SRC_MASK (0x3 << 4)
1070 #define RT5668_I2S2_SRC_SFT 4
1075 #define RT5668_JD1_PULSE_EN_MASK (0x1 << 10)
1078 #define RT5668_JD1_PULSE_EN (0x1 << 10)
1081 #define RT5668_JD1_EN_MASK (0x1 << 15)
1084 #define RT5668_JD1_EN (0x1 << 15)
1085 #define RT5668_JD1_POL_MASK (0x1 << 13)
1087 #define RT5668_JD1_POL_INV (0x1 << 13)
1090 #define RT5668_IL_IRQ_MASK (0x1 << 7)
1092 #define RT5668_IL_IRQ_EN (0x1 << 7)
1098 #define RT5668_GP1_PIN_IRQ (0x1 << 14)
1103 #define RT5668_GP2_PIN_LRCK2 (0x1 << 12)
1108 #define RT5668_GP3_PIN_BCLK2 (0x1 << 10)
1113 #define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8)
1119 #define RT5668_GP5_PIN_DACDAT1 (0x1 << 6)
1121 #define RT5668_GP6_PIN_MASK (0x1 << 5)
1124 #define RT5668_GP6_PIN_LRCK1 (0x1 << 5)
1127 #define RT5668_GP1_PF_MASK (0x1 << 15)
1129 #define RT5668_GP1_PF_OUT (0x1 << 15)
1130 #define RT5668_GP1_OUT_MASK (0x1 << 14)
1132 #define RT5668_GP1_OUT_H (0x1 << 14)
1133 #define RT5668_GP2_PF_MASK (0x1 << 13)
1135 #define RT5668_GP2_PF_OUT (0x1 << 13)
1136 #define RT5668_GP2_OUT_MASK (0x1 << 12)
1138 #define RT5668_GP2_OUT_H (0x1 << 12)
1139 #define RT5668_GP3_PF_MASK (0x1 << 11)
1141 #define RT5668_GP3_PF_OUT (0x1 << 11)
1142 #define RT5668_GP3_OUT_MASK (0x1 << 10)
1144 #define RT5668_GP3_OUT_H (0x1 << 10)
1145 #define RT5668_GP4_PF_MASK (0x1 << 9)
1147 #define RT5668_GP4_PF_OUT (0x1 << 9)
1148 #define RT5668_GP4_OUT_MASK (0x1 << 8)
1150 #define RT5668_GP4_OUT_H (0x1 << 8)
1151 #define RT5668_GP5_PF_MASK (0x1 << 7)
1153 #define RT5668_GP5_PF_OUT (0x1 << 7)
1154 #define RT5668_GP5_OUT_MASK (0x1 << 6)
1156 #define RT5668_GP5_OUT_H (0x1 << 6)
1157 #define RT5668_GP6_PF_MASK (0x1 << 5)
1159 #define RT5668_GP6_PF_OUT (0x1 << 5)
1160 #define RT5668_GP6_OUT_MASK (0x1 << 4)
1161 #define RT5668_GP6_OUT_L (0x0 << 4)
1162 #define RT5668_GP6_OUT_H (0x1 << 4)
1166 #define RT5668_GP6_STA (0x1 << 6)
1167 #define RT5668_GP5_STA (0x1 << 5)
1168 #define RT5668_GP4_STA (0x1 << 4)
1169 #define RT5668_GP3_STA (0x1 << 3)
1170 #define RT5668_GP2_STA (0x1 << 2)
1171 #define RT5668_GP1_STA (0x1 << 1)
1174 #define RT5668_SV_MASK (0x1 << 15)
1177 #define RT5668_SV_EN (0x1 << 15)
1178 #define RT5668_ZCD_MASK (0x1 << 10)
1181 #define RT5668_ZCD_PU (0x1 << 10)
1186 #define RT5668_ZCD_BST1_CBJ_MASK (0x1 << 7)
1189 #define RT5668_ZCD_BST1_CBJ_EN (0x1 << 7)
1190 #define RT5668_ZCD_RECMIX_MASK (0x1)
1193 #define RT5668_ZCD_RECMIX_EN (0x1)
1195 /* 4 Button Inline Command Control 2 (0x00e3) */
1196 #define RT5668_4BTN_IL_MASK (0x1 << 15)
1197 #define RT5668_4BTN_IL_EN (0x1 << 15)
1199 #define RT5668_4BTN_IL_RST_MASK (0x1 << 14)
1200 #define RT5668_4BTN_IL_NOR (0x1 << 14)
1204 #define RT5668_JDH_RS_MASK (0x1 << 4)
1205 #define RT5668_JDH_NO_PLUG (0x1 << 4)
1206 #define RT5668_JDH_PLUG (0x0 << 4)
1209 #define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
1211 #define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
1215 #define RT5668_CKXEN_ADC1_MASK (0x1 << 13)
1217 #define RT5668_CKGEN_ADC1_MASK (0x1 << 12)
1221 #define RT5668_SEL_CLK_VOL_MASK (0x1 << 15)
1222 #define RT5668_SEL_CLK_VOL_EN (0x1 << 15)
1226 #define RT5668_AD2DA_LB_MASK (0x1 << 10)
1230 #define RT5668_NG2_EN_MASK (0x1 << 15)
1231 #define RT5668_NG2_EN (0x1 << 15)
1235 #define RT5668_DEB_STO_DAC_MASK (0x7 << 4)
1236 #define RT5668_DEB_80_MS (0x0 << 4)
1239 #define RT5668_SAR_BUTT_DET_MASK (0x1 << 15)
1240 #define RT5668_SAR_BUTT_DET_EN (0x1 << 15)
1242 #define RT5668_SAR_BUTDET_MODE_MASK (0x1 << 14)
1243 #define RT5668_SAR_BUTDET_POW_SAV (0x1 << 14)
1245 #define RT5668_SAR_BUTDET_RST_MASK (0x1 << 13)
1246 #define RT5668_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1248 #define RT5668_SAR_POW_MASK (0x1 << 12)
1249 #define RT5668_SAR_POW_EN (0x1 << 12)
1251 #define RT5668_SAR_RST_MASK (0x1 << 11)
1252 #define RT5668_SAR_RST_NORMAL (0x1 << 11)
1254 #define RT5668_SAR_BYPASS_MASK (0x1 << 10)
1255 #define RT5668_SAR_BYPASS_EN (0x1 << 10)
1257 #define RT5668_SAR_SEL_MB1_MASK (0x1 << 9)
1258 #define RT5668_SAR_SEL_MB1_SEL (0x1 << 9)
1260 #define RT5668_SAR_SEL_MB2_MASK (0x1 << 8)
1261 #define RT5668_SAR_SEL_MB2_SEL (0x1 << 8)
1263 #define RT5668_SAR_SEL_MODE_MASK (0x1 << 7)
1264 #define RT5668_SAR_SEL_MODE_CMP (0x1 << 7)
1266 #define RT5668_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1267 #define RT5668_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1269 #define RT5668_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1270 #define RT5668_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1271 #define RT5668_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1302 RT5668_DA_STEREO1_FILTER = 0x1,
1303 RT5668_AD_STEREO1_FILTER = (0x1 << 1),