Lines Matching +full:4 +full:x1
41 * The scc2698 contain 4 block.
86 #define MR1_CHRL_6_BITS (0x1 << 0)
89 #define MR1_PARITY_EVEN (0x1 << 2)
92 #define MR1_PARITY_FORCE (0x1 << 3)
96 #define MR1_ERROR_BLOCK (0x1 << 5)
98 #define MR1_RxINT_FFULL (0x1 << 6)
99 #define MR1_RxRTS_CONTROL_ON (0x1 << 7)
104 #define MR2_CTS_ENABLE_TX_ON (0x1 << 4)
105 #define MR2_CTS_ENABLE_TX_OFF (0x0 << 4)
106 #define MR2_TxRTS_CONTROL_ON (0x1 << 5)
109 #define MR2_CH_MODE_ECHO (0x1 << 6)
113 #define CR_ENABLE_RX (0x1 << 0)
114 #define CR_DISABLE_RX (0x1 << 1)
115 #define CR_ENABLE_TX (0x1 << 2)
116 #define CR_DISABLE_TX (0x1 << 3)
117 #define CR_CMD_RESET_MR (0x1 << 4)
118 #define CR_CMD_RESET_RX (0x2 << 4)
119 #define CR_CMD_RESET_TX (0x3 << 4)
120 #define CR_CMD_RESET_ERR_STATUS (0x4 << 4)
121 #define CR_CMD_RESET_BREAK_CHANGE (0x5 << 4)
122 #define CR_CMD_START_BREAK (0x6 << 4)
123 #define CR_CMD_STOP_BREAK (0x7 << 4)
124 #define CR_CMD_ASSERT_RTSN (0x8 << 4)
125 #define CR_CMD_NEGATE_RTSN (0x9 << 4)
126 #define CR_CMD_SET_TIMEOUT_MODE (0xA << 4)
127 #define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
129 #define SR_RX_READY (0x1 << 0)
130 #define SR_FIFO_FULL (0x1 << 1)
131 #define SR_TX_READY (0x1 << 2)
132 #define SR_TX_EMPTY (0x1 << 3)
133 #define SR_OVERRUN_ERROR (0x1 << 4)
134 #define SR_PARITY_ERROR (0x1 << 5)
135 #define SR_FRAMING_ERROR (0x1 << 6)
136 #define SR_RECEIVED_BREAK (0x1 << 7)
140 #define ACR_DELTA_IP0_IRQ_EN (0x1 << 0)
141 #define ACR_DELTA_IP1_IRQ_EN (0x1 << 1)
142 #define ACR_DELTA_IP2_IRQ_EN (0x1 << 2)
143 #define ACR_DELTA_IP3_IRQ_EN (0x1 << 3)
144 #define ACR_CT_Mask (0x7 << 4)
145 #define ACR_CExt (0x0 << 4)
146 #define ACR_CTxCA (0x1 << 4)
147 #define ACR_CTxCB (0x2 << 4)
148 #define ACR_CClk16 (0x3 << 4)
149 #define ACR_TExt (0x4 << 4)
150 #define ACR_TExt16 (0x5 << 4)
151 #define ACR_TClk (0x6 << 4)
152 #define ACR_TClk16 (0x7 << 4)
154 #define ACR_BRG_SET2 (0x1 << 7)
157 #define TX_CLK_110 (0x1 << 0)
169 #define RX_CLK_75 (0x0 << 4)
170 #define RX_CLK_110 (0x1 << 4)
171 #define RX_CLK_38400 (0x2 << 4)
172 #define RX_CLK_150 (0x3 << 4)
173 #define RX_CLK_300 (0x4 << 4)
174 #define RX_CLK_600 (0x5 << 4)
175 #define RX_CLK_1200 (0x6 << 4)
176 #define RX_CLK_2000 (0x7 << 4)
177 #define RX_CLK_2400 (0x8 << 4)
178 #define RX_CLK_4800 (0x9 << 4)
179 #define RX_CLK_1800 (0xA << 4)
180 #define RX_CLK_9600 (0xB << 4)
181 #define RX_CLK_19200 (0xC << 4)
184 #define OPCR_MPOa_C_TO (0x1 << 0)
192 #define OPCR_MPOb_RTSN (0x0 << 4)
193 #define OPCR_MPOb_C_TO (0x1 << 4)
194 #define OPCR_MPOb_TxC1X (0x2 << 4)
195 #define OPCR_MPOb_TxC16X (0x3 << 4)
196 #define OPCR_MPOb_RxC1X (0x4 << 4)
197 #define OPCR_MPOb_RxC16X (0x5 << 4)
198 #define OPCR_MPOb_TxRDY (0x6 << 4)
199 #define OPCR_MPOb_RxRDY_FF (0x7 << 4)
202 #define OPCR_MPP_OUTPUT (0x1 << 7)
204 #define IMR_TxRDY_A (0x1 << 0)
205 #define IMR_RxRDY_FFULL_A (0x1 << 1)
206 #define IMR_DELTA_BREAK_A (0x1 << 2)
207 #define IMR_COUNTER_READY (0x1 << 3)
208 #define IMR_TxRDY_B (0x1 << 4)
209 #define IMR_RxRDY_FFULL_B (0x1 << 5)
210 #define IMR_DELTA_BREAK_B (0x1 << 6)
211 #define IMR_INPUT_PORT_CHANGE (0x1 << 7)
213 #define ISR_TxRDY_A (0x1 << 0)
214 #define ISR_RxRDY_FFULL_A (0x1 << 1)
215 #define ISR_DELTA_BREAK_A (0x1 << 2)
216 #define ISR_COUNTER_READY (0x1 << 3)
217 #define ISR_TxRDY_B (0x1 << 4)
218 #define ISR_RxRDY_FFULL_B (0x1 << 5)
219 #define ISR_DELTA_BREAK_B (0x1 << 6)
220 #define ISR_INPUT_PORT_CHANGE (0x1 << 7)