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Searched +full:48 +full:mhz (Results 1 – 25 of 248) sorted by relevance

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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq9574-rdp-common.dtsi97 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
102 * corner parts to operate at 800MHz
220 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
222 * clock output from WiFi to the CMN PLL is 48 MHZ.
230 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
231 * from WiFi output clock 48 MHZ divided by 2.
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac14 ## 16.384 MHz Unknown audio application
16 ## 22.5792 MHz Redbook/CD
19 ## 24.576 MHz DAT/Video
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
29 ## DAT/video: 24.576 MHz * 1000000 / 512 = 48000Hz
30 ## Redbook/CD: 22.5792 MHz * 1000000 / 512 = 44100Hz
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1447 /* 5 GHz, channels 36..48 */ in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1706 case 1: /* channels 36,40,44,48 */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-nomadik-stn8815.dtsi195 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
205 * The 2.4 MHz TIMCLK reference clock is active at
206 * boot time, this is actually the MXTALCLK @19.2 MHz
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
270 clk48: clk48@48M {
298 hclkdma0: hclkdma0@48M {
304 hclksmc: hclksmc@48M {
310 hclksdram: hclksdram@48M {
316 hclkdma1: hclkdma1@48
[all...]
/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Drs.c28 IWL_DECLARE_RATE_INFO(48),
44 { "48", "64QAM 2/3"},
57 "20Mhz",
58 "40Mhz",
59 "80Mhz",
60 "160 Mhz",
61 "320Mhz",
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsilabs,si5341.txt54 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
99 /* 48MHz reference crystal */
118 silabs,pll-m-den = <48>;
161 /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
H A Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
91 - description: CK_SCMI_FLEXGEN_48 flexgen clock 48
/freebsd/sys/contrib/device-tree/Bindings/mips/cavium/
H A Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h16 * bandwidths <= 80MHz
18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
39 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
42 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
43 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
124 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
125 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
148 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dti,dp83822.yaml87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
105 - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
106 clock frequency is 50-MHz and in RGMII Mode the clock frequency is
107 25-MHz.
109 - 'int-ref': Internal reference clock 25-MHz.
110 - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
113 - 'free-running': Free running clock 125-MHz.
114 - 'recovered': Recovered clock is a 125-MHz recovered clock from a
126 enum: [43, 44, 46, 48, 50, 53, 55, 58, 61, 65, 69, 73, 78, 84, 91, 99]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dda8xx-cfgchip.txt18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h338 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and
467 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes
665 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nuvoton/
H A Dnuvoton-wpcm450.dtsi33 clk24m: clock-24mhz {
34 /* 24 MHz dummy clock */
40 refclk: clock-48mhz {
41 /* 48 MHz reference oscillator */
/freebsd/sys/contrib/device-tree/src/arm/nspire/
H A Dnspire.dtsi110 * 48 for the display so likely the frequency to the
111 * display is 1MHz and the CLCDCLK is 48 MHz.
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmediatek,xsphy.yaml69 mediatek,src-ref-clk-mhz:
95 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
192 mediatek,src-ref-clk-mhz = <26>;
H A Dphy-mtk-xsphy.txt21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
36 "ref": 48M reference clock for HighSpeed analog phy; and 26M
88 mediatek,src-ref-clk-mhz = <26>;
/freebsd/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_3xxx.dts362 /* 12MHz, 24MHz and 48MHz allowed */
382 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c29 /* 20MHz */
38 /* 40MHz */
47 /* 80MHz */
59 /* 20MHz */
68 /* 40MHz */
77 /* 80MHz */
89 /* 20MHz */
96 RADAR_SPEC(2, 60, 15, 48, 940, 2080, 32, 19600, 40200, 32, 0,
98 /* 40MHz */
105 RADAR_SPEC(2, 60, 15, 48, 940, 2080, 32, 19600, 40200, 32, 0,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-iot2050-usb3.dtsi17 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
H A Dk3-am6548-iot2050-advanced-m2-bkey-usb3.dtso37 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
/freebsd/sys/net80211/
H A Dieee80211_regdomain.h55 CTRY_BAHRAIN = 48, /* Bahrain */
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
283 * result and use only the 160 MHz specific version. in verify_channel()
289 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
290 * result and use only the 80 MHz specific version. in verify_channel()
296 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dgcw0.dts123 brightness-levels = <0 16 32 48 64 80 96 112 128
444 * We use a rate of 432 MHz, which is the least common multiple of
445 * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
478 * 750 kHz for the system timer and clocksource, 12 MHz for the OST,
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h278 #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */
279 #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */
280 #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */
281 #define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */
282 #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */
284 #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */
289 #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */
290 #define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */
291 #define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */
292 #define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */
[all …]
/freebsd/sys/dev/iwx/
H A Dif_iwx_debug.c314 printf("(6) 48 Mbps\n"); in print_ratenflags()
343 printf("20MHz "); in print_ratenflags()
346 printf("40MHz "); in print_ratenflags()
349 printf("80MHz "); in print_ratenflags()
352 printf("160MHz "); in print_ratenflags()
355 printf("320MHz "); in print_ratenflags()

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