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/linux/drivers/clk/tegra/
H A Dclk-tegra124-dfll-fcpu.c48 { 204000000UL, { 1112619, -29295, 402 } },
49 { 306000000UL, { 1150460, -30585, 402 } },
50 { 408000000UL, { 1190122, -31865, 402 } },
51 { 510000000UL, { 1231606, -33155, 402 } },
52 { 612000000UL, { 1274912, -34435, 402 } },
53 { 714000000UL, { 1320040, -35725, 402 } },
54 { 816000000UL, { 1366990, -37005, 402 } },
55 { 918000000UL, { 1415762, -38295, 402 } },
56 { 1020000000UL, { 1466355, -39575, 402 } },
57 { 1122000000UL, { 1518771, -40865, 402 } },
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi26 pmu_regs: syscon@402b0000 {
31 aon_regs: syscon@402e0000 {
254 pin_controller: pinctrl@402a0000 {
H A Dsharkl3.dtsi34 pmu_regs: syscon@402b0000 {
51 aon_apb_regs: syscon@402e0000 {
/linux/arch/arm64/boot/dts/freescale/
H A Ds32g2.dtsi183 uart2: serial@402bc000 {
191 usdhc0: mmc@402f0000 {
H A Ds32g3.dtsi240 uart2: serial@402bc000 {
248 usdhc0: mmc@402f0000 {
/linux/Documentation/devicetree/bindings/watchdog/
H A Drenesas,wdt.yaml200 clocks = <&cpg CPG_MOD 402>;
202 resets = <&cpg 402>;
/linux/drivers/net/can/esd/
H A DKconfig3 tristate "esd electronics gmbh CAN-PCI(e)/402 family"
/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c98 DEF_MOD("rwdt", 402, R8A7792_CLK_R),
155 MOD_CLK_ID(402), /* RWDT */
H A Dr8a77470-cpg-mssr.c101 DEF_MOD("rwdt", 402, R8A77470_CLK_R),
164 MOD_CLK_ID(402), /* RWDT */
H A Dr8a77995-cpg-mssr.c148 DEF_MOD("rwdt", 402, R8A77995_CLK_R),
202 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7745-cpg-mssr.c114 DEF_MOD("rwdt", 402, R8A7745_CLK_R),
181 MOD_CLK_ID(402), /* RWDT */
H A Dr8a77970-cpg-mssr.c133 DEF_MOD("rwdt", 402, R8A77970_CLK_R),
168 MOD_CLK_ID(402), /* RWDT */
H A Dr8a77980-cpg-mssr.c138 DEF_MOD("rwdt", 402, R8A77980_CLK_R),
202 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7794-cpg-mssr.c121 DEF_MOD("rwdt", 402, R8A7794_CLK_R),
191 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7791-cpg-mssr.c128 DEF_MOD("rwdt", 402, R8A7791_CLK_R),
210 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7790-cpg-mssr.c140 DEF_MOD("rwdt", 402, R8A7790_CLK_R),
212 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7742-cpg-mssr.c129 DEF_MOD("rwdt", 402, R8A7742_CLK_R),
203 MOD_CLK_ID(402), /* RWDT */
H A Dr8a774c0-cpg-mssr.c166 DEF_MOD("rwdt", 402, R8A774C0_CLK_R),
252 MOD_CLK_ID(402), /* RWDT */
H A Dr8a7743-cpg-mssr.c118 DEF_MOD("rwdt", 402, R8A7743_CLK_R),
197 MOD_CLK_ID(402), /* RWDT */
H A Dr8a77990-cpg-mssr.c168 DEF_MOD("rwdt", 402, R8A77990_CLK_R),
266 MOD_CLK_ID(402), /* RWDT */
/linux/drivers/crypto/intel/qat/qat_4xxx/
H A Dadf_4xxx_hw_data.h38 /* Firmware for 402XXX */
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsprd,sc9860-pinctrl.txt40 pin_controller: pinctrl@402a0000 {
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hip04-net.txt66 interrupts = <0 402 4>;
/linux/include/uapi/sound/intel/avs/
H A Dtokens.h49 AVS_TKN_MODCFG_EXT_TYPE_UUID = 402,
/linux/arch/s390/crypto/
H A Dpaes_s390.c380 .base.cra_priority = 402, /* ecb-paes-s390 + 1 */
560 .base.cra_priority = 402, /* ecb-paes-s390 + 1 */
719 .base.cra_priority = 402, /* ecb-paes-s390 + 1 */

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