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/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
26 Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
35 automatic calibrated position. Two set of 3-tuple setting for each
42 minItems: 3
43 maxItems: 3
53 sampling point. Two set of 3-tuple setting for each supported link speed
59 minItems: 3
60 maxItems: 3
67 Frequency boost AC (LSB 3-bit) and DC (2-bit) gain control. Two set of
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/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h72 /* ports 1-3 follow after this */
79 /* ports 1-3 follow after this */
84 /* ports 1-3 follow after this */
91 /* phys 1-3 follow after this */
94 /* phys 1-3 follow after this */
123 VSR_PHY_MODE11 = 0x0B * 4, /* Event Counter 3 */
144 MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
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H A Dmv_94xx.c48 * R11h -> R120h[31:16] (Generation 3 Setting 0) in set_phy_tuning()
49 * R12h -> R124h[15:0] (Generation 3 Setting 1) in set_phy_tuning()
57 for (i = 0; i < 3; i++) { in set_phy_tuning()
58 /* loop 3 times, set Gen 1, Gen 2, Gen 3 */ in set_phy_tuning()
112 * FFE_CAP_SEL [3:0] in set_phy_ffe_tuning()
152 * FFE_TRAIN_EN 3 in set_phy_ffe_tuning()
159 tmp |= (0 << 3); in set_phy_ffe_tuning()
177 /* support 1.5 Gbps */ in set_phy_rate()
185 /* support 1.5, 3.0 Gbps */ in set_phy_rate()
186 phy_cfg.u.speed_support = 3; in set_phy_rate()
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/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_rate_tc_bw.py39 - Total bandwidth: 1Gbps
81 3: 20.0,
142 {"vlan_id": 101, "tc": 3, "ip": "198.51.100.2"},
214 {"index": 3, "bw": 20},
280 gbps = bits_per_second / 1e9
281 if gbps < min_expected_gbps:
283 f"iperf3 bandwidth too low: {gbps:.2f} Gbps "
284 f"(expected ≥ {min_expected_gbps} Gbps)"
287 return gbps
302 ("198.51.100.2", "198.51.100.1", 3),
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h59 #define FEATURE_DPM_SOCCLK_BIT 3
190 #define THROTTLER_TEMP_MEM_BIT 3
215 #define WORKLOAD_PPLIB_COMPUTE_BIT 3
312 uint8_t Padding[3];
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h79 #define FEATURE_DPM_UCLK_BIT 3
198 #define THROTTLER_TEMP_MEM_BIT 3
222 #define FW_DSTATE_MP0_DS_BIT 3
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
530 XGMI_LINK_RATE_18 = 18, // 18Gbps
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/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
67 #define CFG_0_TX_PAD_EN_SHIFT 3
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
127 #define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
123 data-lanes = <1 2 3 4>;
149 data-lanes = <1 2 3 4>;
H A Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
132 data-lanes = <1 2 3 4>;
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml21 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
22 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
29 The SparX-5 switch family targets managed Layer 2 and Layer 3
137 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
138 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
146 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
147 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
189 minItems: 3
191 minItems: 3
H A Drenesas,ethertsn.yaml14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
124 compatible = "ethernet-phy-ieee802.3-c45";
127 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
318 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
325 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
330 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
335 /* 1.485Gbps, and below */ in meson_hdmi_phy_setup_mode()
405 /* Reset PHY 3 times in a row */ in dw_hdmi_phy_init()
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h139 #define HCLGE_VF_ID_S 3
140 #define HCLGE_VF_ID_M GENMASK(10, 3)
143 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
190 #define HCLGE_SUPPORT_50G_R2_BIT BIT(3)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
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/linux/include/rdma/
H A Dopa_port_info.h30 #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
87 /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
110 #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
119 OPA_PORT_PHYS_CONF_VARIABLE = 3,
217 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
229 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
259 u8 cap; /* 3 res, 5 bits */
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts37 v_3_3: regulator-3-3v {
80 los-gpios = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>;
108 /* SFP+ port 2: 10 Gbps indicator */
114 led-3 {
115 /* SFP+ port 2: 1 Gbps indicator */
117 function-enumerator = <3>;
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c261 /* 3 tries is assumed to be enough to read successfully */ in __intel_cx0_read()
262 for (i = 0; i < 3; i++) { in __intel_cx0_read()
352 /* 3 tries is assumed to be enough to write successfully */ in __intel_cx0_write()
353 for (i = 0; i < 3; i++) { in __intel_cx0_write()
480 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
539 .pll[3] = 0x1,
565 .pll[3] = 0x1,
591 .pll[3] = 0x1,
617 .pll[3] = 0x0,
643 .pll[3] = 0x1,
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/linux/fs/smb/client/
H A Dcifs_debug.c182 return "1Gbps"; in smb_speed_to_str()
184 return "2.5Gbps"; in smb_speed_to_str()
186 return "5Gbps"; in smb_speed_to_str()
188 return "10Gbps"; in smb_speed_to_str()
190 return "14Gbps"; in smb_speed_to_str()
192 return "20Gbps"; in smb_speed_to_str()
194 return "25Gbps"; in smb_speed_to_str()
196 return "40Gbps"; in smb_speed_to_str()
198 return "50Gbps"; in smb_speed_to_str()
200 return "56Gbps"; in smb_speed_to_str()
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/linux/drivers/net/phy/realtek/
H A Drealtek_main.c86 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
99 #define RTL8211F_RX_DELAY BIT(3)
137 #define RTL_VND2_PHYSR_DUPLEX BIT(3)
162 #define RTL8211x_LED_COUNT 3
510 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2])); in rtl8211f_set_wol()
1023 /* bit 3 in rtlgen_decode_physr()
1814 .name = "RTL8226 2.5Gbps PHY",
1825 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1837 .name = "RTL8226-CG 2.5Gbps PHY",
1847 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
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/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
87 ssac = 3; in xhci_create_usb3x_bos_desc()
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
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/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,usb5744.yaml15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
39 3V3 power supply to the hub
99 reset-gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
108 reset-gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c149 if (ipd_port >= 0 && ipd_port <= 3) in cvmx_helper_board_get_mii_address()
166 if (ipd_port >= 0 && ipd_port <= 3) in cvmx_helper_board_get_mii_address()
221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()
256 case 3: /* Illegal */ in __cvmx_helper_board_link_get()
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c123 #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
151 #define MODE_PIPE_WIDTH_32 BIT(3)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
215 #define PHY_PLL_READY_TX_BIT BIT(3)
300 /* 0 1 2 3 4 5 6 7 */
569 /* 3. Use maximum PLL rate (no power save) */ in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c197 * 3: Both Rx and TX flow control (symmetric) is enabled. in igc_force_mac_fc()
329 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); in igc_rar_set()
678 /* For I225, STATUS will indicate 1G speed in both 1 Gbps in igc_get_speed_and_duplex_copper()
679 * and 2.5 Gbps link modes. An additional bit is used in igc_get_speed_and_duplex_copper()
680 * to differentiate between 1 Gbps and 2.5 Gbps. in igc_get_speed_and_duplex_copper()
808 * [0] [1] [2] [3] [4] [5] in igc_hash_mc_addr()
813 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 in igc_hash_mc_addr()
815 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 in igc_hash_mc_addr()
827 case 3: in igc_hash_mc_addr()
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h82 #define H_QPCB0_PORT_NB EHEA_BMASK_IBM(3, 3)
113 #define H_QPCB1_RQ_CQ_HANDLE EHEA_BMASK_IBM(3, 3)
160 #define H_PORT_CB3 3
188 #define H_SPEED_100M_H 3 /* 100 Mbps, Half Duplex */
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
382 #define H_DISABLE_GET_RQC 3
/linux/drivers/ata/
H A DKconfig64 This option will enlarge the kernel by approx. 3KB. Disable it if
121 default 3
147 3 => HIPM (Partial) and DIPM (Partial and Slumber)
285 tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
303 tristate "Freescale 3.0Gbps SATA support"
307 This option enables support for Freescale 3.0Gbps SATA controller.
324 tristate "AMD Seattle 6.0Gbps AHCI SATA host controller support"

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