Lines Matching +full:3 +full:gbps
123 #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
151 #define MODE_PIPE_WIDTH_32 BIT(3)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
215 #define PHY_PLL_READY_TX_BIT BIT(3)
300 /* 0 1 2 3 4 5 6 7 */
569 /* 3. Use maximum PLL rate (no power save) */ in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
643 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. in mvebu_a3700_comphy_ethernet_power_on()
656 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY in mvebu_a3700_comphy_ethernet_power_on()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
716 * PCIe speed 2.5/5 Gbps in mvebu_a3700_comphy_ethernet_power_on()
849 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency in mvebu_a3700_comphy_usb3_power_on()
860 * 3. Set Spread Spectrum Clock Enabled in mvebu_a3700_comphy_usb3_power_on()
956 * 14. Set max speed generation to USB3.0 5Gbps in mvebu_a3700_comphy_usb3_power_on()
1004 /* 3. Force to use reg setting for PCIe mode */ in mvebu_a3700_comphy_pcie_power_on()
1318 if (lane_id >= 3) { in mvebu_a3700_comphy_probe()