48 	* R11h -> R120h[31:16] (Generation 3 Setting 0)  in set_phy_tuning()
49 	* R12h -> R124h[15:0]  (Generation 3 Setting 1)  in set_phy_tuning()
57 	for (i = 0; i < 3; i++) {  in set_phy_tuning()
58 		/* loop 3 times, set Gen 1, Gen 2, Gen 3 */  in set_phy_tuning()
112 	 * FFE_CAP_SEL          [3:0]  in set_phy_ffe_tuning()
152 	 * FFE_TRAIN_EN         3  in set_phy_ffe_tuning()
159 	tmp |= (0 << 3);  in set_phy_ffe_tuning()
177 		/* support 1.5 Gbps */  in set_phy_rate()
185 		/* support 1.5, 3.0 Gbps */  in set_phy_rate()
186 		phy_cfg.u.speed_support = 3;  in set_phy_rate()
192 		/* support 1.5, 3.0, 6.0 Gbps */  in set_phy_rate()
233 		/*set default phy_rate = 6Gbps*/  in mvs_94xx_config_reg_from_hba()
347 		/* 3*4 data bits / PDU */  in mvs_94xx_sgpio_init()
355 		((mvi->id * 4) + 3) << (8 * 3) |  in mvs_94xx_sgpio_init()
408 		/* set 6G/3G/1.5G, multiplexing, without SSC */  in mvs_94xx_init()
411 		/* set 6G/3G/1.5G, multiplexing, with and without SSC */  in mvs_94xx_init()
654 	tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));  in mvs_94xx_command_active()
657 		mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),  in mvs_94xx_command_active()
661 				MVS_COMMAND_ACTIVE + (slot_idx >> 3));  in mvs_94xx_command_active()
1059 		/* maximum supported bits = hosts * 4 drives * 3 bits */  in mvs_94xx_gpio_write()
1060 		for (i = 0; i < mvs_prv->n_host * 4 * 3; i++) {  in mvs_94xx_gpio_write()
1063 			struct mvs_info *mvi = mvs_prv->mvi[i/(4*3)];  in mvs_94xx_gpio_write()
1067 			int drive = (i/3) & (4-1); /* drive number on host */  in mvs_94xx_gpio_write()
1083 			switch (i%3) {  in mvs_94xx_gpio_write()